MainMenu
Tutorial: Schematic Design Flow
This tutorial will introduce you to the features of the ProChip tool that allow
you to create a Schematic File using Altium's (formerly Protel Inc.) Design
Explorer 99SE by walking you through the Compilation and Fitting process of
one of the Example files included with the Product. This tutorial also allows
you to use the Schematic Editor tool to add more functionality to the Design.
Step I: Create a Sample Project using New Project Wizard
Step II: Add a Schematic File and overview of Schematic Editor
Step III: Modify the Schematic File
Step IV: Compile(Synthesize) the Schematic Module
Step V: Use ATMEL Fitter to fit Synthesized Design File
Tutorial: CUPL Design Flow
This tutorial will introduce you to the features of the ProChip tool that allow
you to create a Schematic File using Altium's (formerly Protel Inc.) Design
Explorer 99SE by walking you through the Compilation and Fitting process of
one of the Example files included with the Product. This tutorial also allows
you to use the Schematic Editor tool to add more functionality to the Design.
Step I: Create a Sample Project using New Project Wizard
Step II: Add a CUPL File
Step III: Modify the CUPL File
Step IV: Compile(Synthesize) the CUPL Module
Use ATMEL Fitter to fit Synthesized Design File
Tutorial 1: Altium VHDL Design Flow
This tutorial will introduce you to the features of ProChip Designer software with the Altium
PeakFPGA used as the VHDL synthesis and simulation tools by walking you through the
Synthesis, Place-and-Route and Simulation processes of an example VHDL Project included
with the software.
Step I : Create a Project Using the "New Project Wizard"
Step II : Add a VHDL Design File
Step III : Synthesize the VHDL Design
Step IV : Place-and-route the Synthesized Design File
Step V : Functional Simulation
Tutorial: VHDL Design Flow with LeonardoSpectrum
This tutorial will introduce you to the basic features of the ProChip Designer software with
Mentor Graphics LeonardoSpectrum used as the VHDL synthesis tool. You will be going
through step-by-step the synthesis and device fitting processes of an example VHDL project
included with the software. Before starting this tutorial, you MUST have LeonardoSpectrum properly installed and the Atmel CPLD library setup as specified in the instructions provided in the ProChip Designer Installation Guide.
Step I : Create a Project Using the "New Project Wizard"
Step II : Add a VHDL Design File
Step III : Synthesize the VHDL Design
Step IV : Place-and-route the Synthesized Design File
Tutorial: CPLD Design Flow Tutorial
This tutorial will guide you through a complete design cycle for the Atmel ATF15xx CPLD with Logic Doubling
architecture. It will step-by-step go through each phase of the design cycle from design entry, logic synthesis, device fitting, in-system programming, and finally verifying the design on the Atmel CPLD Development/Programming Board.
Note: To complete this tutorial, ProChip Designer V4.0 or later and Atmel-ISP Software (ATMISP) V4.0 or
later are required.
I : Create a Project using ProChip Designer's New Project Wizard
II : Add a Design File
III : Compile the Design
IV : Fit the Synthesized Design File
V : Program and Verify Design
Converting ABEL Design Files to CUPL
Converting Xilinx Coolrunner Designs to Atmel ATF15xx low power Family of CPLDs.
Converting ABEL Design Files to CUPL
Installation Guide for ProChip Designer 4.0
© Atmel Corporation
The fitter controls
JTAG:
JTAG: Default setting is ON. The device will turn on the ISP port [4 pins are reserved for the JTAG port].
TDI Pull-up Default is Off. When turned ON, the setting enables weak pull up on TDI pin.
TMS Pull-up Default is Off. When turned ON, the setting enables weak pull up on TMS pin.
In order to enable the weak pull up Resistors on TDI, TMS, the JTAG option box must have a .
Power Save:
Pin Power Down 1,2 Default setting is Off for Standard power devices. Use this option to use PD1 or the PD2 pin to power down the device to standby mode (Icc is less than 1 mA).
Auto Wake Default setting is Off for Standard power devices. Devices that have the low power feature such as the ATF15xxL should use this feature to further reduce the Icc (power consumption) since low power devices have Input transition Detection [ITD] circuitry..
GCK1, GCK2, GCK3 Wake Default setting is OFF. This enables ITD on Global clock pin. When turned off, the ITD circuitry is disabled. The device will thus not wake up on a transition on a GCK pin and thus minimize power consumption.
Simulation:
Generate Sim Files A check in this box indicates that simulation files for Post Route Simulation are generated. Useful for VHDL flow and if user has created a test bench file.
Security:
Secure Part: The default setting is Off. Enable this option if you want to generate a JEDEC (programming file) with the Security bit [set].
More fitter controls
Power Reset:
Large Hysteresis This is the default selection. Also helps in reducing the Standby power, especially for low voltage devices. Power Cycling requires that you power up from below 0.7 V.
Small Hysteresis The device has a single voltage level below which the Chip will be Reset. Not recommended for Low Voltage devices.
Pin Fit Control:
Keep Preassignments are always kept.
Ignore Preassignments are ignored.
Try (Default Choice.) Preassignments are kept whenever possible
Device Logic Options:
Pin Keeper: The default setting will enable the Pin Keeper Circuits on all Inputs and I/Os. Floating pins will thus be at known states [either logic high or low]
Optimize: The default setting is Enabled. When this feature is enabled, the fitter will perform the XOR Synthesis, Node Collapsing, Foldback and Cascade Logic optimization strategies to fit the design. If this feature is disabled, the fitter will use no logic reduction strategies and map the design logic exactly as written in the source file.
Latch Synthesis: The default setting is disabled. When enabled, the Fitter tries to implement a Combinatorial Latch using the Latch provided in the Macrocell.
Global Reset: Use GCLEAR to reset the flip flops.
Logic Double:
if necessary: allows the Device fitter to use Logic doubling if it helps to pack in more logic
always: The Fitter will try to implement Logic doubling features.
Logic doubling allows user to implement Combinatorial Latches while using the Buried latch available in a Macrocell. Individual Output Enable control, Dual independent feedback paths for buried and pin feedback paths are key logic doubling features.
Logic nodes / Fitter
Logic Node Defaults
These are default settings for all Nodes. If individual control is desired , please click on the Pin/Node optimization Tab (Advanced options)
Fast Input: Default setting is Off. When turned on, it allows for fast setup times to a D Flip Flop within a Macrocell and thus improves timing performance.
Power Save: Default setting is Off. When turned on, all Macrocells operate in a reduced power mode. There is a speed penalty. If the Reduced power option box is left unchecked, then the Speed of the device increases.
Fast Slew Rate: The Fast Slew Rate for all Outputs property allows the user to specify all outputs in the design to switch at a fast slew rate. The default setting for this property is Disabled. When this property is enabled all output pins will operate at maximum speed. If this property is disabled, all outputs will switch at a slow slew rate. Pins that use slow slew rate help in reducing switching noise.
Soft Buffer: The fitter has a node collapsing feature which attempts to collapse as many combinatorial nodes as possible to minimize resource usage. The Soft Buffer property, when enabled, will prevent the fitter from collapsing all nodes in a design. If this feature is disabled, (default setting) all nodes in the design may be collapsed at the fitters discretion.
Enable Foldback: Enables Foldback logic to be used for all Macrocells in a Logic Array Block. This is a general setting which allows the Fitter to use Foldback nodes if available.
Force Foldback: Defines a node(s) as a Foldback node in a Logic Array Block.
Enable Cascade: Enables Cascade feature on all outputs in the Design.
Enable XOR Synthesis: The XOR synthesis property when enabled, allows the fitter to use this reduction strategy for all pin and nodes in the design. If this property is disabled (default setting) the fitter will attempt the map the logic in a sum of products form.The fitter employs various strategies to reduce design logic to map into the hardware XOR gate within the device and can lead to efficient resource usage for Comparison or Arithmetic logic designs.
Open Collector: Allows an output to be configured as an Open collector. If unchecked (default), the output is a normal output.
Global Output Enable: Use GOE[0-5] to enable the Buffers. The Signal that feeds the most TRI state buffers is chosen as one of the global OE signals.
Schematic tutorial
ATMEL-PROCHIP DESIGNER™
Tutorial: Schematic Design Flow
This tutorial will introduce you to the features of the ProChip tool that allow
you to create a Schematic File using Altium's (formerly Protel Inc.) Design
Explorer 99SE by walking you through the Compilation and Fitting process of
one of the Example files included with the Product. This tutorial also allows
you to use the Schematic Editor tool to add more functionality to the Design.
Step I: Create a Sample Project using New Project Wizard
Step II: Add a Schematic File and overview of Schematic Editor
Step III: Modify the Schematic File
Step IV: Compile(Synthesize) the Schematic Module
Step V: Use ATMEL Fitter to fit Synthesized Design File
Step I: Create a Sample Project using New Project Wizard
Step I: Create a Sample Project using New Project Wizard
The Prochip Designer tool has a built in Wizard that shows Designers a very easy way of
creating a Project file (File with extension .APJ). This Project file must be created prior
to starting the Design process.
After installation of Prochip Designer System (via a CD or directly from the Atmel
website), the PC desktop will have an Icon for 'Prochip' as well as 'Protel 99 Atmel
Edition' as shown in Fig. 1. These short-cuts allow the user to launch the tools in a
seamless manner.
Note:
Users are not recommended to launch the Atmel edition of Protel 99SE tool unless they
want to target devices that are not part of the Prochip Device selection menu.
Fig. 1
1. Click on the START….PROGRAMS……Prochip4.0 Icon as shown in Fig. 2
to launch Prochip OR double-click on the PROCHIP icon on the desktop (see
Fig. 1).
Fig. 2
2. Click on the PROJECT.......NEW or on the Shortcut button as shown in Fig. 3.
Fig. 3
3. This will launch the NEW PROJECT WIZARD to guide the users through the
project creation process. Click on the Next button (Fig. 4) to start the process of
creating a PROJECT FILE.
Fig. 4
4. Click on the BROWSE button to open the browser window as shown in Fig. 5.
Use \PROCHIP\DESIGNS\SCH\LCD as the directory of the project. Enter
LCD.APJ as the project file name. The extension of a project file must be .APJ.
Fig. 5
The name and directory of the design project is specified in this window. All design,
simulation, and other project files must be placed in this project directory.
5. Choose a Part for the Project [ATF1502AS-7JC44]. Also review the Filters that
allow for selection of a specific or a Package type. The Device in the
Part Number field must be highlighted in order to go to the next step in the
Wizard as shown in Fig. 6.
Fig. 6
Select the Project
directory and enter
the Project name
6. Select Schematic-Altium as the Software tool for this Design flow.
Fig. 7
With ProChip Designer V4.0 and later, the five possible design flows and their
corresponding design entry types supported are listed in the table below:
Design Flow Design Entry Type
CUPL - Altium CUPL design entry through Altium Protel Design Explorer 99SE
Verilog - Exemplar* Verilog design entry through Exemplar Leonardo Spectrum
VHDL - Altium VHDL design entry through the Altium PeakFPGA
VHDL - Exemplar* VHDL design entry through Exemplar Leonardo Spectrum
Schematic - Altium Schematic design entry through Altium Protel Design Explorer 99SE
• Requires Mentor Graphics Leonardo Spectrum software with Atmel CPLD support.
Table 1
7. Click on the !"#$% Done with Parts Button as shown in Fig. 8. The User has the
option of including more parts to the current Project Directory. Click once again
on the Next button.
Fig. 8
8. Proceed to click on the Finish Button to complete the New Project
Wizard and the project creation process.
9. This closes the New Project Wizard and opens the Prochip Designer Window.
The Sources in the Project are shown in the Left window in Fig. 9. The Source
Manager, Logic Synthesis and other Processes are listed in the Left window.
Fig. 9
All Project files created by a process reside under the directory structure of the
Process window. You may then click on the + or - buttons to view the files.
Device
Icon
10. Click on the Device Icon as shown in Fig. 9 [ATF1502AS-7JC44] to view the
Design Flow as shown in Fig. 10. All Design processes for the Prochip Designer
tool are shown in the Design Flow window.
Fig. 10
11. Click on the Device View Tab to view the Device architecture of the device.
Fig. 11
This completes Step 1 of this Tutorial.
Step II: Add a Schematic File and overview of Schematic Editor
Step II: Add a Schematic File and Brief overview of Schematic Editor
Schematic capture is the process of capturing a design as a schematic in a computer-aided
design environment. In Altium's Design Explorer Tool (launched through the Atmel
Prochip Designer Interface), the basic workspace for capturing a schematic is called a
schematic sheet. A complete circuit design can use just a single sheet, or it can comprise
a number of electrically linked sheets. Altium (Protel) allows you to create complex
hierarchical and modular designs by linking any number of sheets to form a complete
project.
The Focus of this exercise is to use the Tool to work with Schematics for Programmable
Logic. Once the Project file is created, the next step is to add the Design Source file(s)
into your project. For this tutorial, we will be adding a single Schematic Design file into
the Project.
1. Click on the ADD/EDIT button from the SOURCE MANAGER to open the
Source Manager window. You can also view the Source Manager Help File by
clicking on the Help button within the Source Manager Window to view the
description for different processes.
Fig. 11
Click on the ADD button to add an Altium (Protel) Schematic File to the Project. Select
the LCD.sch file since this is the Source Schematic file.
2. As soon as you click on the 'ADD' button you will see the Altium Design
Explorer 99SE tool being launched (This will do some processing and then
automatically close). This process can take a few seconds. In this process, Prochip
is setting up its environment since the Altium Schematic tool is one of the several
third party tool interfaces.
Fig. 12
3. Select the LCD.sch file (file is highlighted). Once a file is selected, the EDIT tab
becomes visible. Click once on the EDIT tab to launch Altium's Design
Explorer 99SE tool. Once the Altium tool is launched, Prochip interface remains
in the background. It is possible to view or edit the Schematic files in the Altium-
Design Explorer 99SE environment.
Please note that for users who have previously used Altium's tools or are current
users, it is possible to launch the Atmel edition of the tool directly without going
through the Prochip Designer interface. This is useful if you are targeting an Atmel
EPLD that is not directly supported via the Prochip Designer interface. When
launched independently (Simply click on the Atmel Edition of Protel 99SE tool from
the Start programs menu), users will be required to create a .DDB file (MS access
database format file).
Working with documents & folders in a design
Using Design Explorer to manage documents and folders within a design database is
very similar to using the Windows Explorer to manage files and folders on your hard
disk. There are, however important differences. Documents within a design database
do not exist as separate files on the hard disk. They are fully stored within the database
structure, which is contained in the .DDB design database file.
4. After the Schematic Editor window opens, the file is ready for editing. Fig. 13
shows a snapshot view of the Altium Schematic Design environment.
Fig. 13
5. Altium Schematic Editor Features> Viewing Toolbars:
Click on View .…..Toolbars from the Design Explorer Main Menu. Click once
on Toolbars and select Wiring Tools as shown in Fig. 14.
For ATMEL-PLD Schematics, you will only require the Wiring tool to draw and
place your Symbols.
{Please note that all Symbols are from the generic Pldsymbols.ddb library}
This library includes all the functional blocks required to create a schematic.
Project
Sources in
LCD.ddb
Use the Wiring
Toolbar to create
the Schematic
Fig. 14
The Wiring Tool Bar is shown as an active toolbar in Fig.15. One may similarly activate
the PLD Toolbar but this is not required, unless you want to view the Pin Assignments in
the Source File.
Fig. 15
To view or assign pin assignments, click once on the 'LOC' button within the
"PLDTools" toolbar. It is also possible to customize so that only the toolbars of
relevance to the Atmel EPLDs for schematic flow can be displayed to allow the designer
to quickly complete the source design.
To customize, click once on View .…..Toolbars from the Design Explorer Main Menu.
With 'Toolbars' option highlighted, select the 'Customize..' option.
Fig. 16
Fig. 16 shows the available toolbars.
6. Managing Schematic Components and Using the Symbol Library
Schematic component descriptions are stored in schematic libraries, which can be
stored within a design database or as external files named with a .LIB extension.
The default schematic libraries supplied with Atmel edition of Protel 99 SE are
stored within a series of design databases located in the Design Explorer 99
SE\Library\Sch folder in your Protel installation directory. Components are
created and modified in the schematic library editor, an independent document
editor that includes tools for managing and editing libraries. You can open a
schematic sheet and the schematic library editor simultaneously.
Fig. 17 shows how a user can view the libraries available for designing a
schematic.
To access the components in the schematic
libraries, the libraries must first be added to the
list of available libraries in the schematic sheet
editor.
To view a list of currently available libraries, set
the Browse scope to Libraries in the
schematic panel. A list of currently loaded
libraries will be shown. Click on a library name
in the list to show a list of all components it
contains in the lower list box.
To add libraries to the available libraries list,
click the Add/Remove button on the panel, or
select Design » Add/Remove Library from
the menus. This opens the Change Library List
dialog, where libraries can be added and
removed from the Current File List. Once
libraries have been added, parts from those
libraries can be placed on the sheet.
Fig. 17
Use the PLDSymbols.lib only for creating designs that target the ATF15xx family of
devices. The Symbol libraries shown are specific to the Atmel version of Design
Explorer Tool. For a more comprehensive library for other vendors, please contact
Altium International.
The symbols used to create a schematic representation of PLDs are found in the PLD
Symbols .Lib schematic library file. There are over 360 symbols in this library, covering
all standard functional groups, such as buffers, comparators, flip-flops, and so on, as well
as symbols for defining the connections to the physical pins of the PLD device.
Note: It is important that you are familiar with the architecture of the device that your
design is targeted for, to ensure that you only use symbols that can be implemented in
that device.
The symbols are named in one of two ways. Most are named using a set of descriptors,
with different letters to indicate the various functions supported by that symbol. The
others are named using standard TTL 74 series logic names. These are preceded with the
letter X, for example X74_138.
7. Setting Sheet Options and Preferences for the Schematic:
The Schematic preferences affect the schematic editing environment .To set the
schematic environment preferences you must have a schematic sheet as the active
document. Select Tools » Preferences [shortcut T P] from the menu to open the
Preferences dialog as shown in Fig. 18
Fig. 18
The bottom Right Side of the Schematic Sheet shows the Strings for
Organization, documentation, address, Time, Date. These Strings can be
modified and the information for your Organization can be shown here by
clicking on the 'Graphical Editing Tab' and inserting a Check for 'Convert
Special Strings' as shown in Fig. 18. Fig. 19 show an example of entering
Information for the String Information for your Organization.
Fig. 19
o Use schematic electrical design objects to define all circuit elements.
o Use schematic drawing objects to define any non-electrical objects
that you want to appear on your schematic sheet.
To set the options for the active schematic sheet, select Design » Options from
the menus to open the Document Options dialog. This dialog has two tabs:
Sheet Options tab - In this tab you configure the sheet size and orientation,
border style, title block, grid ranges, background color, and system font.
Click one on Design Options..and verify that the Schematic Sheet Size is set to
SIZE B (17.00 IN x 11.00 IN) as shown in Fig. 20. You can increase the size of
the sheet by choosing a different Size or go with Standard A4 size.
Fig. 20
8. Interfacing from internal PLD logic to component pins
Special input (IPAD), output (OPAD), and input/output (IOPAD) symbols are
used to interface from the internal logic to the pins of the target programmable
device. These symbols are available from the PLD Symbols.Lib schematic library
file. Place one of the appropriate pad symbols at each point that connects to a
component pin, and give each PAD symbol a unique designator.
To define the pin number of the component that the pad connects, double-click on
the pad symbols on the schematic to open its properties dialog. In the Part Fields
1-8 tab of the properties dialog, enter a value into the first part field using the
following syntax:
LOC=PIN[pin_number]
where pin_number is the device pin number you wish to connect to. For example,
to specify that the pad connects to pin 7 of the device, enter LOC=PIN[7] into
the symbol's part field.
The syntax for defining the pins of a multiple pad symbols is as follows:
LOC=PIN[pin_1, pin_2,...,pin_n]
where pin_1 is the pin number for the first pad, pin_2 is the pins number for the
second pad, etc.
This completes Step II.
Step III: Modify the Schematic File
Step III: Modify the Schematic File
1. In this section, use the EDITOR to modify the LCD.sch file. Use the
PLDSYMBOLS library to add the following components:
• 3-Input AND Gate {AND3B2 - is a 3-input AND gate with 2 bubbles
(inverted).
• An IBUF (Input buffer) and an OBUF (Output Buffer)
• A D-type Flip flop {FD} which is clocked with signal GCLK already
shown in the LCD.sch schematic
• An IPAD and OPAD
• Change text in the Schematic from g22v10 to f1502plcc44 ( ATF1502ASPLCC44)
Assign the following Pin numbers:
Pin12 to Signal D2, Pin 33 to NOUT,
Change U6 for signal D0 from Pin 2 to Pin 6,
Change signal D1 from Pin 3 to Pin 7.
Change the U1 Clock Signal from Pin 1 to pin 2.
2. Brief Review of the Hot Buttons required to modify the Schematic is shown
in Fig. 21.
Use schematic electrical design objects to
define all circuit elements. (Basically this
means use Icons from the Wiring Tool Bar)
Toolbar: Wiring tools - Menu: Place »
Wire [P W]
Description: A wire forms an electrical
connection between points on a schematic
Note: A wire is an electrical object and
should ONLY be used to make electrical
connections between points on a
schematic. To draw a non-electrical line
on a schematic, use the Line object.
Action Mouse Keyboard
General
To place object (or vertex of complex object).
Left-Click ENTER
Quit current mode. Right-Click ESC
Toolbar: Wiring tools - Menu: Place »
Part
Description: A part is a schematic
symbol.
To place: Once in part placement mode, a
Zoom In/Out - PG UP/PG DN
Flip object along the x-axis. - X
Flip object along the y-axis. - Y
Edit properties of object currently on cursor -
TAB
Rotate the object currently on the cursor -
SPACE BAR
representation of the part will appear
floating on the cursor. Position and rotate
the part using the keyboard shortcut keys.
Left-click or press ENTER to place the
part. Continue placing other parts of the
same type, or right-click or press ESC to
exit part placement mode.
Press the TAB key during placement to
edit the object's properties.
Net label (Schematic electrical design object)
Toolbar: Wiring tools - Menu: Place » Net
Label [P N]
Description: A net label assigns a particular
net name to an electrical object. When a net list
is generated, default names will be given to
each net in the schematic. Manually placing a
net label on your schematic defines the name
of the net to which it is attached.
To place: Once in net label placement mode,
position the cursor so that it touches the object
to which you want to assign the label. Left click
or press ENTER to place the label.
Continue placing further net labels, or right click
or press ESC to exit placement mode.
Press the TAB key during placement to edit
the object's properties.
Graphical editing: When a net label is in
focus, one can Click anywhere within the
dashed box to "pick up" the net label and
reposition it.
Junction
Toolbar: Wiring tools Menu: Place »
Junction [P J]
Description: A junction forms an
electrical connection where two or more
wires cross. A junction is automatically
inserted when a wire starts or terminates
anywhere along the length of another
wire. When a wire crosses other wires, no
junction is inserted. If you want to create a
connection between crossed wires, place a
junction at the crossing point.
To place: Once in junction placement
mode, simply left-click or press ENTER
to place a junction at the cursor position.
Right-click or press ESC to exit junction
placement mode.
Press the TAB key during placement to
edit the object's properties.
Graphical editing: When a junction is in
focus one can Click anywhere within the
dashed box to "pick up" the junction and
reposition it
Fig. 21
3. By default, the part fields for schematic components are generally hidden. For
input, output or IO PLD pad symbols, however, you can easily show or hide the
pin assignment statements on your schematic. To toggle the pin assignment
statements between hidden and displayed, from the schematic select PLD »
Toggle Pin LOC from the menus.
4. Zoom into the left portion of the Schematic by clicking on the + Icon from the
Main Tool Bar.
Fig. 21
The Schematic currently shows the IPAD with certain Designators. Note that
each Symbol that is placed in the Schematic must have a Name.
For e.g.
The Input Pad Symbol U6 [Name]
chosen has a Pin Number assigned as
Pin 7.
To disable View, click on PLD...Toggle
Pin LOC as shown in Figure 22.
Alternatively one can access the same
menu item from the PLD Tool Bar.
Fig. 22
5. Adding Library components
Before we Proceed, ensure that you have enough Room in your schematic to add
additional components. You can use the Zoom button to view the Schematic.
!! Check if you have already re sized your Sheet Size from B to C , thus enlarging
it.
Click on the Gate Symbol from within the Wiring Toolbar as shown in Fig. 23.
Fig. 23
6. This brings up the PLACE PART User Interface. Click on Browse to view the
Different Part Types. In this step we will add all the components required and
then proceed to interconnect them. This brings up the Browse Schematic Library
box as shown in Fig. 24
Fig. 24
7. Click on the Add/Remove button to view the Libraries that are available for
adding. See Fig. 25
Fig. 25
For this Tutorial, verify that the PLD.ddb library is seen as a Selected File. It
should be visible in the bottom half of the Screen snapshot. If not, proceed to add
the PLD.ddb. Note: It is possible to add/remove libraries of Components.
Click on the Cancel button to view the Symbols for the PLD.ddb library of
Components. Select the AND3B2 symbol as shown in Fig. 26
Fig. 26
8. Click once on Close. This immediately brings up the Place Part box. Change the
Designator Field from U? to U100 as shown in Fig. 27. Click on OK.
Fig. 27
9. This immediately places a Symbol on the Cursor. Proceed to the top half of your
Schematic sheet and place the component by clicking once on the Schematic
sheet. See Fig. 28
Fig. 28
10. As soon as you are done with placing this AND3B2 component, the Place Part
box User Interface box shows up. The Designator filed in this box automatically
increments to 101. However since we do not need another of the AND3B2
components, you may click on Browse to select the FD symbol (D type Flip
Flop). Place this to the right side of the AND3B2 component. The FD Symbol
thus has the designator U101.
Similarly place an OBUF (U102), IBUF (assign designator U103) , IPAD
(U104) and OPAD (U105) as shown in Fig. 29. Note the User can always choose
these designators in any order.
Fig. 29
11. Drawing a Wire
To place: Once in wire placement mode, left-click or press ENTER to anchor the
starting point for the wire, then position the mouse and left-click or press ENTER
to anchor a series of vertex points that define the shape of the wire. When you
have finished drawing the wire, right-click or press ESC.
Click once on the WIRE component to interconnect the Pins as shown in Fig.
30.{You may refer to the Table in Fig. 21 that lists the different Hot buttons}
Fig. 30
12. Repeat the previous steps to draw another wire object, or right-click or press ESC
to exit wire placement mode. Complete wiring of all the components as shown in
Fig. 31.
Fig. 31
13. Proceed to complete the Wiring Process as shown in Fig. 32.
One input D0 must also be routed to the Bubble input of the AND3B2 symbol.
Tap a line (you can use a Junction). The other input of this AND (AND3B2) gate
must be connected to the Output of the OR Gate (U31) as shown in Fig. 32.
Note that U31 is a 3 input OR gate shown in the right hand side of the
Schematic.
Fig. 32
14. Assigning Names (Net Name)
Assign Net name D2 to the Input Signal U104. Similarly assign a Net name
GCLK for the Clock input of the D Register (Fig. 33).
Refer to the Net Label button description listed in the Hot button section of this
tutorial. (Fig. 21)
Fig. 33
15. Assign a Net name for the output of the AND gate. Name it 'INTER'.
Assigning Pin Numbers
Click on the PLD Toolbar to "Toggle Pin LOC". This allows you to see all the
Pin assignments associated with various signals as shown in Fig. 34.
Fig. 34
16. Double click on the [*] with the Cursor next to the LOC button . This will launch
the properties box (fig. 35) and will allow one to assign specific pin numbers.
Fig. 35
Assign pin
numbers in
this text box
You can now assign Pins12 to Signal D2, Pin 33 to NOUT
Change existing assignment :
Change U6 for signal D0 from Pin 2 to Pin 6,
Change signal D1 from Pin 3 to Pin 7.
Also change the Clock Signal (U1) Pin from pin 1 to pin 2.
17. Change the text Description from Device=g22v10 to f1502plcc44 in the main
Schematic sheet.
Fig. 36
18. Select the text box by double clicking anywhere within the box. This brings up
the Annotation box. Type the information in the text box. See Fig. 37
Fig. 37
19. Verify that you have completed the Pin assignments defined in Step III - 1.
20. Click on Save button within Atmel Edition of Design Explorer 99SE to Save
your Schematic project file. Then proceed to Close the Design Explorer tool
by clicking once on the x button.
21. This completes Step III. Now proceed to Step IV - Compiling the Schematic
File
Step IV: Compile(Synthesize) the Schematic Module
Step IV: Compile(Synthesize) the Schematic Module
Since our Target devices are the ATF15xx family, we will use the Design Flow
from the Prochip Design Tool to compile the Schematic and generate a .PLA file
which is required for the Device Fitter.
Note:
Once a schematic-based PLD design is complete, you can also run the PLD compiler
directly from the schematic to produce the JEDEC source file used to program the PLD.
The general setup of the PLD compiler options is the same as for a CUPL-based PLD
design. See Compiling a PLD design in the Design Explorer 99 Help section for
information on setting the general compiler options. There are, however, specific compiler
options that pertain only to schematic-based designs.
If your PLD design uses multiple schematic sheets, you must set the Net Identifier Scope
of the PLD compiler to correctly identify the sheet hierarchy. From the schematic select
PLD » Configure from the menus. In the Options tab of the Configure Advanced PLD
dialog, select the correct Net Identifier Scope from the drop down list. See the topic
Connectivity in a mufti-sheet schematic design in the Design Explorer 99SE Tool for
details of the various scope options. If you wish to include all sheets of a mufti-sheet
design in the compile, uncheck the Current Sheet Only option. From the schematic, select
PLD » Compile the PLD compilation process. The design is first translated from a
schematic to a CUPL compiler source file. The resulting CUPL document
(file name.PLD) is then compiled to produce the selected output files.
1. After completion of Step 3, the Design Explorer SE Tool closes and returns you
to the Prochip Designer Tool flow (Fig. 38).
Fig. 38
2. Click on the Compile Logic {Logic Synthesis} Button. This opens the Logic
Synthesis Window.
Fig. 39
3. Click on CUPL options (Click on the CUPL TAB as seen in Fig. 39) from within
the Logic Synthesis Process to view the CUPL Compiler strategies. Verify that
Minimization is set to Quick and Optimization has no Checks in any box.
4. Summary of CUPL strategies can be viewed in the Help file.
Minimization levels
Quine-McCluskey and Presto will perform multiple
output minimization in PLD devices. This maximizes
product term sharing in these types of devices.
Enabling None defeats all logic minimization during
a compilation. It is useful when you want to keep
contained product terms from being eliminated.
Expresso provides a higher level of reduction
efficiency. It requires more memory to compile than
Presto, but requires less time for compilation.
Optimization
Best for Polarity: This is useful if
User knows the Device
architecture of the Target device.
XOR Equations is useful for XOR
Synthesis.
Demorgan: This use
Demorganisation to implement a
logic equation using Sum of
Products or vice versa.
5. Logic Synthesis requires an Input File (LCD.sch). Synthesis will convert the
Schematic Source code (LCD.sch)into a PLA file (LCD.tt2). Synthesis runs the
Compilation process by translating the Schematic File first into a .PLD (CUPL)
Source file. Any errors in this process require the user to go back into the
Schematic Editor and view the Listing files.
Output: LCD.PLA (.TT2) file. This file will be used by the Device Fitter.
Click on the Compile button. This immediately launches the Design Explorer
Environment and if the Compilation is successful, Success is indicated.
All Compilation is done with the Virtual Device type. Individual Device mnemonics can
also be specified from within the Design Explorer Tool.
Fig. 40
6. Close the Design Explorer 99 Window and return to the Design Flow of Prochip
Designer tool. If a box pops up requesting you to save the updated Schematic File,
click on Yes and proceed to save the Schematic File.
This completes Step 4 of this tutorial.
Step V: Use ATMEL Fitter to Fit the Synthesized Design File
Step V: Use ATMEL Fitter to Fit the Synthesized Design File
1. In Step IV we completed the Logic Synthesis portion of the Design Flow. Upon
successful compilation, a PLA output file (with extension .pla/.tt2) is produced by the
Altium CUPL synthesis tool.
2. A .PLA file is an optimized net list of the minimized logic equations that were
generated for a virtual device type by the Compiler. We now need to map this net list
into a specific Atmel PLD architecture using the Atmel fitter.
Proceed to the Device Fitter portion of the Design Flow (Fig. 38).
In Step 2, we completed the Logic Synthesis portion of the Design Flow.
Upon successful compilation, a PLA output file (with extension .pla/.tt2) is
produced by the Altium CUPL synthesis tool.
3. Click once to launch the Device Fitter Window (Fig. 41). Normally you can use the
Default options to fit the Design.
Fig. 41
4. Click once on the Global Device Tab and review the Fitter strategies.
Fig. 42
Verify that Pin Fit Control is set to Keep. Also click on Pin/Node optimization to
review the pin assignments.
5. Click on the RUNFITTER button. Review the FITTER Report file and verify that
the Pin assignments match the Schematic Pin Assignments and use the Jedec file to
program an ATF1502AS in PLCC package.
6. The Report File is a scrollable window, meaning you can view the Pin assignments in
the Screen shot shown above. This completes Step 5.
7. Congratulations on Completion !! You are now ready to begin Designing with
ATMEL PLDs using the Schematic Editor.
CUPL tutorial
ATMEL-PROCHIP DESIGNER™
Tutorial: Schematic Design Flow
This tutorial will introduce you to the features of the ProChip tool that allow
you to create a Schematic File using Altium's (formerly Protel Inc.) Design
Explorer 99SE by walking you through the Compilation and Fitting process of
one of the Example files included with the Product. This tutorial also allows
you to use the Schematic Editor tool to add more functionality to the Design.
Step I: Create a Sample Project using New Project Wizard
Step II: Add a CUPL File
Step III: Modify the CUPL File
Step IV: Compile(Synthesize) the CUPL Module
Use ATMEL Fitter to fit Synthesized Design File
Step I: Create a Sample Project using New Project Wizard
Step I: Create a Sample Project using New Project Wizard
The Prochip Designer tool has a built in Wizard that shows Designers a very easy way of
creating a Project file (File with extension .APJ). This Project file must be created prior
to starting the Design process.
After installation of Prochip Designer System (via a CD or directly from the Atmel
website), the PC desktop will have an Icon for 'Prochip' as well as 'Protel 99 Atmel
Edition' as shown in Fig. 1. These short-cuts allow the user to launch the tools in a
seamless manner.
Note:
Users are not recommended to launch the Atmel edition of Protel 99SE tool unless they
want to target devices that are not part of the Prochip Device selection menu.
Fig. 1
1. Click on the START….PROGRAMS……Prochip4.0 Icon as shown in Fig. 2
to launch Prochip OR double-click on the PROCHIP icon on the desktop (see
Fig. 1).
Fig. 2
2. Click on the PROJECT.......NEW or on the Shortcut button as shown in Fig. 3.
Fig. 3
3. This will launch the NEW PROJECT WIZARD to guide the users through the
project creation process. Click on the Next button (Fig. 4) to start the process of
creating a PROJECT FILE.
Fig. 4
4. Click on the BROWSE button to open the browser window as shown in Fig. 5.
Use \PROCHIP\DESIGNS\SCH\LCD as the directory of the project. Enter
LCD.APJ as the project file name. The extension of a project file must be .APJ.
Fig. 5
The name and directory of the design project is specified in this window. All design,
simulation, and other project files must be placed in this project directory.
5. Choose a Part for the Project [ATF1502AS-7JC44]. Also review the Filters that
allow for selection of a specific Speed grade or a Package type. The Device in the
Part Number field must be highlighted in order to go to the next step in the
Wizard as shown in Fig. 6.
Fig. 6
Select the Project
directory and enter
the Project name
6. Select Schematic-Altium as the Software tool for this Design flow.
Fig. 7
With ProChip Designer V4.0 and later, the five possible design flows and their
corresponding design entry types supported are listed in the table below:
Design Flow Design Entry Type
CUPL - Altium CUPL design entry through Altium Protel Design Explorer 99SE
Verilog - Exemplar* Verilog design entry through Exemplar Leonardo Spectrum
VHDL - Altium VHDL design entry through the Altium PeakFPGA
VHDL - Exemplar* VHDL design entry through Exemplar Leonardo Spectrum
Schematic - Altium Schematic design entry through Altium Protel Design Explorer 99SE
Requires Mentor Graphics Leonardo Spectrum software with Atmel CPLD support.
Table 1
7. Click on the nmlkj Done with Parts Button as shown in Fig. 8. The User has the
option of including more parts to the current Project Directory. Click once again
on the Next button.
Fig. 8
8. Proceed to click on the Finish Button to complete the New Project
Wizard and the project creation process.
9. This closes the New Project Wizard and opens the Prochip Designer Window.
The Sources in the Project are shown in the Left window in Fig. 9. The Source
Manager, Logic Synthesis and other Processes are listed in the Left window.
Fig. 9
All Project files created by a process reside under the directory structure of the
Process window. You may then click on the + or - buttons to view the files.
Device
Icon
10. Click on the Device Icon as shown in Fig. 9 [ATF1502AS-7JC44] to view the
Design Flow as shown in Fig. 10. All Design processes for the Prochip Designer
tool are shown in the Design Flow window.
Fig. 10
11. Click on the Device View Tab to view the Device architecture of the device.
Fig. 11
This completes Step 1 of this Tutorial.
Step II: Add a CUPL File
Step II: Add a CUPL File
Schematic capture is the process of capturing a design as a schematic in a computer-aided
design environment. In Altium's Design Explorer Tool (launched through the Atmel
Prochip Designer Interface), the basic workspace for capturing a schematic is called a
schematic sheet. A complete circuit design can use just a single sheet, or it can comprise
a number of electrically linked sheets. Altium (Protel) allows you to create complex
hierarchical and modular designs by linking any number of sheets to form a complete
project.
The Focus of this exercise is to use the Tool to work with Schematics for Programmable
Logic. Once the Project file is created, the next step is to add the Design Source file(s)
into your project. For this tutorial, we will be adding a single Schematic Design file into
the Project.
1. Click on the ADD/EDIT button from the SOURCE MANAGER to open the
Source Manager window. You can also view the Source Manager Help File by
clicking on the Help button within the Source Manager Window to view the
description for different processes.
Fig. 11
Click on the ADD button to add an Altium (Protel) Schematic File to the Project. Select
the LCD.sch file since this is the Source Schematic file.
2. As soon as you click on the 'ADD' button you will see the Altium Design
Explorer 99SE tool being launched. This process can take a few seconds. In this
process, Prochip is setting up its environment since the Altium Schematic tool is
one of the several third party tool interfaces.
Fig. 12
3. Select the LCD.sch file (file is highlighted). Once a file is selected, the EDIT tab
becomes visible. Click once on the EDIT tab to launch Altium's Design
Explorer 99SE tool. Once the Altium tool is launched, Prochip interface remains
in the background. It is possible to view or edit the Schematic files in the Altium-
Design Explorer 99SE environment.
Please note that for users who have previously used Altium's tools or are current
users, it is possible to launch the Atmel edition of the tool directly without going
through the Prochip Designer interface. When launched independently, users will be
required to create a .DDB file (MS access database format file). When a Project is first
opened, users will be asked if Files are to be
Step III: Modify the CUPL File
Step III: Modify the CUPL File
1. In this section, use the EDITOR to modify the LCD.sch file. Use the
PLDSYMBOLS library to add the following components:
3-Input AND Gate {AND3B2 - is a 3-input AND gate with 2 bubbles
(inverted).
An IBUF (Input buffer) and an OBUF (Output Buffer)
A D-type Flip flop {FD} which is clocked with signal GCLK already
shown in the LCD.sch schematic
An IPAD and OPAD
Assign the following Pin numbers:
VHDL tutorial
ProChip Designer - VHDL Quick-Start Tutorial P. 1
ATMEL-PROCHIP DESIGNER
Tutorial 1: Altium VHDL Design Flow
This tutorial will introduce you to the features of ProChip Designer software with the Altium
PeakFPGA used as the VHDL synthesis and simulation tools by walking you through the
Synthesis, Place-and-Route and Simulation processes of an example VHDL Project included
with the software.
Step I : Create a Project Using the "New Project Wizard"
Step II : Add a VHDL Design File
Step III : Synthesize the VHDL Design
Step IV : Place-and-route the Synthesized Design File
Step V : Functional Simulation
Step I: Create a Project using the "New Project Wizard"
Step I: Create a Project using the "New Project Wizard"
Before the design process can be started, a Project File must be created. The ProChip
Designer's New Project Wizard gives designers a very easy way to create a Project File.
1. Click on the START….PROGRAMS….PROCHIP Icon to launch ProChip Designer.
Or double-click on the PROCHIP icon on the desktop.
(1) Click to launch
ProChip Designer
ProChip Designer - VHDL Quick-Start Tutorial P. 2
2. Click on PROJECT .... NEW or double-click on the NEW PROJECT shortcut button to
launch the New Project Wizard.
3. Click on the NEXT button to start the project file creation process.
4. Click on the BROWSE button to open the browser window.
5. Use C:\PROCHIP\DESIGNS\VHDL as the directory of the project.
6. Enter SHIFT.APJ as the project file name. The extension of a project file must be .APJ.
The name and directory of the design project is specified in this window. All design,
simulation, and other project files must be placed in this project directory.
(2) Click to
create new
project
(3) Click NEXT
to start
(5) Select the project
directory
(6) Enter the project
file name
(4) Click on
BROWSE
ProChip Designer - VHDL Quick-Start Tutorial P. 3
7. Choose a device for the project. [ATF1502AS-7AC44]. Also review the Filters that allow
for selection of a specific Speed Grade or Package Type.
8. Select VHDL - ALTIUM as the software tool for this design flow.
With ProChip Designer V4.0 and later, the five possible design flows and their corresponding
design entry types supported are listed in the table below:
(7) Select the
device type
(8) Select the
design flow
ProChip Designer - VHDL Quick-Start Tutorial P. 4
Design Flow Design Entry Type
CUPL - Altium CUPL design entry through Altium Protel Design Explorer 99SE
Verilog - Mentor Graphics* Verilog design entry through Mentor Graphics LeonardoSpectrum
VHDL - Altium VHDL design entry through the Altium PeakFPGA
VHDL - Mentor Graphics* VHDL design entry through Mentor Graphics LeonardoSpectrum
Schematic - Altium Schematic design entry through Altium Protel Design Explorer 99SE
* Requires Mentor Graphics Leonardo Spectrum software with Atmel CPLD support.
9. Select DONE WITH PARTS so that there will be only one device in this project.
On the other hand, users can select ADD MORE PARTS to include more parts to the
current Project Directory.
10. Click the FINISH button to finish the New Project Wizard and the project creation process.
This closes the New Project Wizard and opens the ProChip Designer window. The Sources
in the project are shown in the Left window.
(9) Select "Done
with parts"
(10) Click FINISH
to end New
Project Wizard
ProChip Designer - VHDL Quick-Start Tutorial P. 5
11. Click on the Device Icon [ATF1502AS-7AC44] to view the Design Flow.
This completes Step I of this Tutorial.
Project Sources Window Information Dialog Box
Message Log Window Project Device Icon
Design Flow Window Project File Window
ProChip Designer - VHDL Quick-Start Tutorial P. 6
Step II: Add a VHDL Design File
Step II: Add a VHDL Design File
Once the Project File is created, the next step is to add the design source file(s) into your project.
For this tutorial, we will be adding a single-level hierarchy VHDL design file into the project.
1. Click on the ADD/EDIT button from Source Manager to open the Source Manager Window.
You can view the Source Manager Help File by clicking on the Help button within the
Source Manager Window to view the description for the different processes.
2. In the Source Manager Window, click on the ADD button to add a VHDL design file to the
project.
3. In the File Manager Window, select SHIFTER.VHD from the [~\Prochip\designs\vhdl]
directory as the source design file for this project.
The Source Manager Window must have all source VHDL files included with the first file as the
Top-Order VHDL file. You should not include Test bench files in the Source Manager Window.
When adding files, ensure that Top-Down order is maintained. Ordering of the design files can
be arranged in the ProChip Project Window by drag-and-drop the files into the appropriate
location after all the files are added through the Source Manager.
4. To edit the VHDL design file, first select the VHDL file (SHIFT.VHD) that you want to edit
in the Source Manager window.
(1) Click Add/Edit
to open Source
Manger
Window
(2) Click Add
to add
design file
(3) Select
VHDL
source file
ProChip Designer - VHDL Quick-Start Tutorial P. 7
5. Click on the EDIT button to view the VHDL file using the Atmel HDL Planner Editor.
This shift register VHDL design has an 8-bit data input and an 8-bit data output. The registers are
asynchronously reset using the Rst input. When Rst is not active, the registers shift (rotate) one
bit to the left whenever there is a rising edge detected on the Clock (CLK) input.
After reviewing the 8-bit Barrel Shifter example, click on the OK button and proceed to the
LOGIC SYNTHESIS portion of the Design Flow.
You have now completed Step II of this Tutorial.
(4) Select
VHDL
source file
(5) Click Edit
to edit
source file
HDL Planner
Editor Window
ProChip Designer - VHDL Quick-Start Tutorial P. 8
Step III: Synthesize the VHDL Design
Step III: Synthesize the VHDL Design
In this step, you will synthesize your VHDL design into optimized/minimized logic equations
through the Altium VHDL synthesis tool (Metamor).
1. Click on the VHDL - METAMOR button in the Design Flow Window to open the Logic
Synthesis Window.
2. Click on the COMPILE button to start the VHDL Synthesis process.
Logic Synthesis requires an Input File: Shifter.vhd (VHDL Source File)
Action: Synthesis will compile the VHDL Source code into an EDIF file. The default tool is
Altium Metamor Synthesis tool. Synthesis is a straightforward process, particularly when
dealing with a single VHDL source file. The result of Synthesis is an EDIF net list, which is used
by the Device Fitter to place and route your design.
Output: Shifter.EDF file. This will be the Top-level VHDL file name.edf. Examine the options
available and proceed to compile your source file. You may refer to the HELP file for more
description.
(1) Launch Logic
Synthesis tool
(2) Start the
Synthesis
process
ProChip Designer - VHDL Quick-Start Tutorial P. 9
Upon the completion of the synthesis process, the synthesis LOG and/or the net list EDIF files
will open in NOTEPAD as shown below if the "view file when compiled" options are checked in
the Logic Synthesis window.
The EDIF Version supported is 2.00
This completes Step III of this Tutorial.
ProChip Designer - VHDL Quick-Start Tutorial P. 10
Step IV: Use ATMEL Fitter to Fit the Synthesized Design File
Step IV: Use ATMEL Fitter to Fit the Synthesized Design File
In Step III, we completed the Logic Synthesis portion of the Design Flow. Upon successful
compilation, an EDIF output file (with extension .edf) is produced by the VHDL synthesis tool.
An EDIF file contains the net list of the optimized and minimized logic equations. We now need
to map this net list into a specific Atmel PLD architecture using the ATMEL FITTER.
1. You can now proceed to the Device Fitter portion of the Design Flow by clicking on the
ATMEL FITTER button.
You can either use the Default options or specify Fitter properties. Without an EDIF file
selected, the Fitter will not run. In this example, since our target device is an ATF1502AS, the
Tool selected will be the FIT1502.EXE device fitter.
Output files created are JEDEC (.JED) and a FITTER REPORT (.FIT) file. Both these files are
important for you to figure out the Pin assignments for Board Layout and for programming the
Device (In-system or on a Third Party Device Programmer)
(1) Open the
Atmel Fitter
Window
ProChip Designer - VHDL Quick-Start Tutorial P. 11
Please review the Global Device Parameters and Pin/Node Options as well. The Help Files also
show the Device Pin_Node lists for each of the ATMEL CPLDs.
Check the box for GENERATE SIM FILES. The files required for Post-Route Timing [Timing
Simulation] are .VHO and .SDO.
.VHO is a VHDL Output file and .SDO is a Standard Delay Output Format file. At the
minimum, you only need a VHDL Source file for you to generate a JEDEC file and program a
device.
2. When all the fitter options are set, click on the RUN FITTER button to fit the design.
(2) Start the
fitting process
Check "Generate
Sim Files"
ProChip Designer - VHDL Quick-Start Tutorial P. 12
The Fitter Report File is shown below.
This completes Step IV of this Tutorial.
ProChip Designer - VHDL Quick-Start Tutorial P. 13
Step V: Functional Simulation
Step V: Functional Simulation
In this step, you will do a functional simulation of your VHDL design to verify the functionality
of your design. Your VHLD design will be simulated by applying stimulus to your design
through the VHDL Test bench.
1. Click on the ADD/EDIT button in the Test bench Manager box of the Design Flow to add a
Test bench File to the design project.
2. In the Test bench Manager Window, click ADD to add a Test bench file into your project.
3. In the File Selection Window, select TESTSHIF.VHD in the
C:\PROCHIP\DESIGNS\VHDL directory as the VHDL Test bench.
4. Now you can start the VHDL simulator by clicking the VHDL - PEAKFPGA button in the
Functional Simulation box within the Design Flow.
5. In the Functional Simulation Window, click on the "+" mark next to the Test bench file
(testshif.vhd), select TESTROT as the Test bench, and then click on the SIMULATE button
to open the simulator with the selected Test bench file loaded.
(2) Click to open
Test bench
Manager
(3) Click ADD to
add Test bench
(4) Select the
Test bench file
ProChip Designer - VHDL Quick-Start Tutorial P. 14
You must first select/highlight the Test bench File before clicking on the SIMULATE button in
the Functional Simulation Window.
The Test bench File must be associated with the source VHDL file specified in the Source
Manager.
Now the PeakFPGA tool (VHDL synthesis and simulation) opens and the appropriate Design
and Test bench files will be loaded automatically as shown below.
6. Click on the REBUILD HIERARCHY button and then select the TESTSHIF.VHD file.
Note that the Project Name has now changed to SHIFT_PRE.ACC. The .ACC extension is used
by the Altium Simulation tool to remember the hierarchy.
(5) Click on the
VHDL -
PeakFPGA
button
(6) Select the
Test bench and
click Simulate
Test bench File
Source Design File
ProChip Designer - VHDL Quick-Start Tutorial P. 15
7. Click on the LINK button. A transcript window opens behind the scenes and a shifter.vx file,
which is the simulation executable, is created.
8. Click on LOAD SELECTED SIMULATION button (this button is located next to the
LINK button) to start the simulator.
9. In the SELECT DISPLAY OBJECTS WINDOW, click on the ADD ALL button to view
the waveforms for all the signals. Then click on the CLOSE button to close this window.
The ADD ALL button adds all the signals in the Available Objects Window to the waveform.
The ADD PRIMARIES button adds all signals found in the highest level of your design to the
waveform.
You can use the UP, DOWN buttons to arrange order of the signals to be displayed in the
waveform.
(6) Click on the
Rebuild Hierarchy
button
Select
TESTSHIF.VHD
(7) Click on the
Link button
(8) Click on the Load
Selected Simulation
button
(9) Select Add All
Then Close to
close window
ProChip Designer - VHDL Quick-Start Tutorial P. 16
You only need to select and order the signals once for a given project. By default, the simulator
remembers your most recent signal selections and ordering, and if needed, you can also use the
Save Objects and Load Objects feature to save specific collections of object names and
orderings.
As you can see, the VHDL SIMULATOR window is split into four distinct panes. The top-most
two panes are the Object Display and Waveform windows, respectively. These two windows
are linked for scrolling purposes, and provide you with an up-to-date view of the value (in both
text and waveform formats) of the value of each object you selected previously. Features of these
windows include the ability to zoom and pan through the waveform, drop measurement cursors
and rearrange objects (in terms of their vertical display order) at will.
The center window is the Source Code Display window. This window shows the current line of
code that is being executed in your VHDL design. This window is also where you set
breakpoints. A drop-down list of source files (located up in the toolbar) allows you to select
alternate source files for setting of breakpoints. Single-step features (also controlled from the
toolbar) let you advance simulation one line at a time and see the results in the Source Code
Display and Waveform windows.
The bottom-most window is the Transcript window. This window displays simulator status
messages, and also displays any text I/O output (entered as statements in your VHDL code) that
are directed to the console. VHDL assertion/report statements also appear in this window.
10. Before proceeding with Simulation, click on the SIMULATION OPTIONS button.
Waveform
window
Object Display
window
Source Code
Display window
Transcript
window
(10) Open
Simulation Options
ProChip Designer - VHDL Quick-Start Tutorial P. 17
Vector display format This option specifies how mufti-bit VHDL values (vectors) are to be
displayed. Valid options are binary, octal, decimal and
hexadecimal.
Time unit This option specifies the default time unit to be displayed in
simulation waveforms.
Run to time This option specifies the default end time for simulation. This is the
time value to which the simulator will advance when started using
the Go button. (This value can be changed from within the VHDL
simulator interface if needed.)
Step time This option specifies the default step time. This is the amount of
time that the simulator will advance when the Step button is
selected. (This value can be changed from within the VHDL
simulator interface if needed.)
Max signal depth This option allows you to control how deeply in the hierarchy the
simulator should go when extracting and displaying signals for
possible viewing. For simulation models such as post-route models,
this option can speed the time needed for the simulator to load your
design. [ This is not really relevant for this Tutorial]
ProChip Designer - VHDL Quick-Start Tutorial P. 18
11. To start the simulation process and advance the time to the previously specified simulation
end time (the Run to time), click on the green GO button.
As the simulation progresses, the current simulation time is displayed in the status bar at the
bottom of the application frame, and status messages (if any) are displayed in the Transcript
window.
After the simulation has finished, a waveform showing the simulation results is displayed as
shown below:
At this point you may be satisfied with the results of simulation (as shown in the Waveform
window), or you may need to investigate the results further. The VHDL simulator has various
features allowing more detailed analysis. For example, you can use the Source Code Display
window to set one or more break points in the code to investigate the control flow through your
design.
The Step button is useful for advancing simulation by a predetermined amount of time, such as
one or more clock cycles. For this project, we have previously set the Step time to 100ns. The
Step time value and other simulation values can be changed at any time by selecting the Options
dialog from within the VHDL simulator.
We can set a Break point as shown above [Notice the red ball icon at line 49] and then press the
Step button until this break point is triggered. Note that a break point can also be set by double clicking
on the line in the window or using the menu.
If you wish to advance the simulator one source file line at a time (to investigate control flow
through conditional statements, for example), you can use the Single-Step buttons (Step Over
and/or Step Into). We could set additional break points, or we could compare the results of
(11) Click on the
Go button
Simulation
results
Break point
is set
ProChip Designer - VHDL Quick-Start Tutorial P. 19
simulation (the values seen on various signals and variables) against our expectations to track
down logic problems.
The VHDL simulator has other features that are documented in the on-line help. For now,
however, let's assume that this design is working as expected and move on to the Post-route
Timing Simulation phase of the tutorial. You can close the VHDL simulator application window
at this point.
This completes Step V of this Tutorial and this is the end of this VHDL Tutorial.
Tutorial: VHDL Design Flow with LeonardoSpectrum
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 1
ATMEL-PROCHIP DESIGNER
Tutorial: VHDL Design Flow with LeonardoSpectrum
This tutorial will introduce you to the basic features of the ProChip Designer software with
Mentor Graphics LeonardoSpectrum used as the VHDL synthesis tool. You will be going
through step-by-step the synthesis and device fitting processes of an example VHDL project
included with the software.
Before starting this tutorial, you MUST have LeonardoSpectrum properly installed and the
Atmel CPLD library setup as specified in the instructions provided in the ProChip Designer
Installation Guide.
Step I : Create a Project Using the "New Project Wizard"
Step II : Add a VHDL Design File
Step III : Synthesize the VHDL Design
Step IV : Place-and-route the Synthesized Design File
Instructions on how to setup Atmel CPLD libraries in LeonardoSpectrum:
----------------------------------------------------------------------
1. Copy $Prochip\Leonardo_update\cpld.syn to
$MGC\LeoSpec\LS2002c_49\lib directory
2. Copy $Prochip\Leonardo_update\atmlcpld.ini to
$MGC\LeoSpec\LS2002c_49\lib directory
3. Copy $Prochip\Leonardo_update\cpld.vhd to
$MGC\LeoSpec\LS2002c_49\data\modgen directory
4. Copy the text from below to the appropriate place in
$MGC\LeoSpec\LS2002c_49\lib\devices.ini
a)-Attach the line below to the end of device declaration section. The device number "179" is the last device number plus one. If the last device number in original devices.ini file is a different number than "178", the device number should be change to appropriate number.
DEVICE_179=atmel_cpld
b)-Attach the lines below to the end of devices.ini file.
[atmel_cpld]
CONTACT=EPLD Applications\nATMEL Corporatn\n2325 Orchard Parkway\nSan Jose, CA 95131\n\nTel: (408) 436-4333\nFax: (408) 436-4200\nEmail: pld@atmel.com
DIRECTION=BOTH
FAMILY=CPLD
FORM=FPGA
HTML_PAGE=http://www.atmel.com
INI_FILE=atmlcpld
LIBRARY_NAME=cpld
LICENSE_PACKAGE_NAME=atmel
MANUFACTURER=Atmel
NUMBEROFPASSES=4
PROPTIONS=FALSE
SYMBOL_LIBRARY=none
TECHNOLOGY_TYPE=FPGA
VENDOR_NAME=ATMEL Corporation
BMPFILE=atmel16.bmp
Note:
$Prochip points to the directory where Prochip is installed on your machine
$MGC points to the directory where Leonardo Spectrum is installed on your machine.
Step I: Create a Project using the "New Project Wizard"
Step I: Create a Project using the "New Project Wizard"
Before the design process can be started, a Project File must be created. The ProChip
Designer's New Project Wizard gives designers a very easy way to create a Project File.
1. Click on the START….PROGRAMS….PROCHIP Icon to launch ProChip Designer.
Or double-click on the PROCHIP icon on the desktop.
(1) Click to launch
ProChip Designer
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 2
2. Click on PROJECT .... NEW or double-click on the NEW PROJECT shortcut button to
launch the New Project Wizard.
3. Click on the NEXT button to start the project file creation process.
4. Click on the BROWSE button to open the browser window.
5. Use C:\PROCHIP\DESIGNS\VHDL as the directory of the project.
6. Enter SHIFT.APJ as the project file name. The extension of a project file must be .APJ.
The name and directory of the design project is specified in this window. All design,
simulation, and other project files must be placed in this project directory.
(2) Click to create
new project
(3) Click NEXT
to start
(5) Select the project
directory
(6) Enter the project
file name
(4) Click on
BROWSE
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 3
7. Choose a device for the project. [ATF1502AS-7AC44]. Also review the Filters that allow
for selection of a specific Speed Grade or Package Type.
8. Select VHDL - Mentor Graphics as the software tool for this design flow.
With ProChip Designer V4.0 and later, the five possible design flows and their corresponding
design entry types supported are listed in the table below:
(7) Select the
device type
(8) Select the
design flow
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 4
Design Flow Design Tool Type
CUPL - Altium CUPL design entry through Altium Protel Design Explorer 99SE
Verilog - Mentor Graphics* Verilog design entry through Mentor Graphics LeonardoSpectrum
VHDL - Altium VHDL design entry through the Altium PeakFPGA
VHDL - Mentor Graphics* VHDL design entry through Mentor Graphics LeonardoSpectrum
Schematic - Altium Schematic design entry through Altium Protel Design Explorer 99SE
* Requires Mentor Graphics LeonardoSpectrum software with a mufti-vendor Level 3 license.
9. Select DONE WITH PARTS so that there will be only one device in this project.
On the other hand, users can select ADD MORE PARTS to include more parts to the
current Project Directory.
10. Click the FINISH button to finish the New Project Wizard and the project creation process.
This closes the New Project Wizard and opens the ProChip Designer window. The Sources
in the project are shown in the Left window.
(9) Select "Done
with parts"
(10) Click FINISH
to end New
Project Wizard
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 5
11. Click on the Device Icon [ATF1502AS-7AC44] to view the Design Flow.
This completes Step I of this Tutorial.
Project Sources Window Information Dialog Box
Message Log Window Project Device Icon
Design Flow Window Project File Window Tool Configuration button
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 6
Step II: Add a VHDL Design File
Step II: Add a VHDL Design File
Once the Project File is created, the next step is to add the design source file(s) into your project.
For this tutorial, we will be adding a single-level hierarchy VHDL design file into the project.
1. Click on the ADD/EDIT button from Source Manager to open the Source Manager Window.
You can view the Source Manager Help File by clicking on the Help button within the
Source Manager Window to view the description for the different processes.
2. In the Source Manager Window, click on the ADD button to add a VHDL design file to the
project.
3. In the File Manager Window, select SHIFTER.VHD from the [~\Prochip\designs\vhdl]
directory as the source design file for this project.
The Source Manager Window must have all source VHDL files included with the first file as the
Top-Order VHDL file. You should not include Test bench files in the Source Manager Window.
When adding files, ensure that Top-Down order is maintained. Ordering of the design files can
be arranged in the ProChip Project Window by drag-and-drop the files into the appropriate
location after all the files are added through the Source Manager.
4. To edit the VHDL design file, first select the VHDL file (SHIFT.VHD) that you want to edit
in the Source Manager window.
(1) Click Add/Edit
to open Source
Manger Window
(2) Click Add
to add design
file
(3) Select
VHDL source
file
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 7
5. Click on the EDIT button to view the VHDL file using the Atmel HDL Planner Editor.
This shift register VHDL design has an 8-bit data input and an 8-bit data output. The registers are
asynchronously reset using the Rst input. When Rst is not active, the registers shift (rotate) one
bit to the left whenever there is a rising edge detected on the Clock (CLK) input.
After reviewing the 8-bit Barrel Shifter example, close the HDL Planner window and proceed to
the LOGIC SYNTHESIS portion of the Design Flow.
You have now completed Step II of this Tutorial.
(4) Select
VHDL source
file
(5) Click Edit
to edit source
file
HDL Planner
Editor Window
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 8
Step III: Synthesize the VHDL Design
Step III: Synthesize the VHDL Design
In this step, you will synthesize your VHDL design into optimized/minimized logic equations
through the Mentor Graphics LeonardoSpectrum VHDL synthesis tool.
1. Click on the VHDL - Leonardo button in the Design Flow Window to open the Logic
Synthesis Window.
2. Click on the COMPILE button to launch LeonardoSpectrum.
3. In the LeonardoSpectrum window, go to the Tools menu and enable the Quick Setup setting
or click on the Quick Setup button. This setting allows the user to very easily and quickly
setup the LeonardoSpectrum software to synthesize the target design.
4. In the Technology dialog box, choose FPGA/CPLD Atmel CPLD to target the
VHDL design into the Atmel CPLD (ATF15xx) device.
(1) Launch Logic
Synthesis tool
(2) Click on COMPILE
to launch
LeonardoSpecdtrum
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 9
5. The Input, Output files and the Working Directory settings are automatically entered into
the LeonardoSpectrum software by ProChip Designer. Therefore, the next step would be to
click on the Run Flow button to synthesize the VHDL design.
When the synthesis process is completed successfully, you can then exit the LeonardoSpectrum
software.
Upon the completion of the synthesis process, the synthesis LOG and/or the net list EDIF files
will open in NOTEPAD as shown below if the "view file when compiled" options are checked in
the Logic Synthesis window.
(4) Select Atmel
CPLD library
(3) Select "Quick
Setup"
(5) Click "Run Flow"
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 10
The EDIF Version supported is 2.00
This completes Step III of this Tutorial.
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 11
Step IV: Place-and-route the Synthesized Design File
Step IV: Place-and-route the Synthesized Design File
In Step III, we completed the Logic Synthesis portion of the Design Flow. Upon successful
compilation, an EDIF output file (with extension .edf) is produced by the VHDL synthesis tool.
An EDIF file contains the net list of the optimized and minimized logic equations. We now need
to map this net list into a specific Atmel PLD architecture using the ATMEL FITTER.
1. You can now proceed to the Device Fitter portion of the Design Flow by clicking on the
ATMEL FITTER button.
You can either use the Default options or specify Fitter properties. Without an EDIF file
selected, the Fitter will not run. In this example, since our target device is an ATF1502AS, the
Tool selected will be the FIT1502.EXE device fitter.
Output files created are JEDEC (.JED) and a FITTER REPORT (.FIT) file. Both these files are
important for you to figure out the Pin assignments for Board Layout and for programming the
Device (In-system or on a Third Party Device Programmer)
(1) Open the
Atmel Fitter
Window
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 12
Please review the Global Device Parameters and Pin/Node Options as well. The Help Files also
show the Device Pin_Node lists for each of the ATMEL CPLDs.
Check the box for GENERATE SIM FILES. The files required for Post-Route Timing [Timing
Simulation] are .VHO and .SDO.
.VHO is a VHDL Output file and .SDO is a Standard Delay Output Format file. At the
minimum, you only need a VHDL Source file for you to generate a JEDEC file and program a
device.
2. When all the fitter options are set, click on the RUN FITTER button to fit the design.
(2) Start the
fitting process
Check "Generate
Sim Files"
ProChip Designer - LeonardoSpectrum VHDL Quick-Start Tutorial P. 13
The Fitter Report File is shown below.
This completes this Tutorial.
Converting ABEL Design Files to CUPL
Converting ABEL Design Files to CUPL
This application note is intended to assist users in converting designs written in ABELHDL
language to CUPL. It also includes an example in ABEL and equivalent representation
in CUPL. Atmel® no longer offers ABEL compilers. Instead users are
encouraged to convert their designs to CUPL and use Atmel Design software tools
such as Atmel-WinCUPL™ or ProChip Designer™.
Background for ABEL and CUPL
ABEL-HDL and CUPL-HDL are behavioral design languages used to describe logic
circuits at a high level. ABEL evolved over the eighties and early nineties as a language
that was written to take advantage of the architectural features of an EPLD. As
late as 1995, Atmel continued to offer ABEL V5.1 (DOS-based program). This
required a Dongle (Key from Data I/O™ Corp. WA) to be plugged into the parallel port
of a PC. Subsequently, Atmel offered an EDA package called Atmel-Synario™ that
included a windows version of the ABEL compiler until the year 2000. Atmel-Synario
V4.11 was an OEM version specific for Atmel EPLDs and ABEL 6.5 (windows version)
was the last version of ABEL-HDL offered by Atmel as part of this package. Subsequently,
Data I/O spun off Synario as an EDA company and a little later Synario's
assets became a part of MINC Inc., another EDA Company. MINC then re-sold specific
tools from the Synario package to Xilinx®, Inc.
Logical Devices, Inc. developed CUPL and the structure of the language has not
changed much for the last two decades. Atmel offered a DOS version of CUPL until
the late nineties. The most recent DOS version of Atmel-WinCUPL shipped by Atmel
was Rev 4.8. Subsequently a windows version of CUPL (Rev 5.x) was offered and
called Atmel-WinCUPL.
ABEL/CUPL
Design File
Conversion
Application
Note
Rev. 3303A-PLD-08/02
2 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Compiler and Tool
Options
The CUPL compiler is available in Atmel-WinCUPL Version 5.2.16 software as well as
part of Atmel-ProChip Designer that uses a Third Party tool from Altium™ called Design
Explorer™ 99SE.
For simple designs, users are encouraged to use Atmel-WinCUPL which is a free tool
and available for download from Atmel's website.
The ABEL compiler (Rev. 6.5) used to compile the ABEL example was part of Atmel-
Synario Version 4.11 software, which is no longer offered.
Process of Conversion of
an ABEL Example File to
CUPL
The conversion is presented in the form of a Table (Table 1) and shows comparative
implementation in ABEL and CUPL. Users can first go through this example and then
refer to "Overview of Syntax Differences between ABEL and CUPL" on page 7 for Syntax
details. Simulation files are not required for every design unless users specifically
want to functionally generate a set of Test Vectors that can be applied on a Third Party
Programmer hardware. The process of writing Test vector files is listed in the section
titled "Converting an ABEL Simulation Input File to CUPL" on page 5.
Please note that in ABEL, it is possible to include Test vectors as part of the main
source file. The ABEL compiler will then extract the test vectors (.TMV) for simulation
purposes and to append the test vectors to the Jedec file.
Description of Example The following example in Table 1 shows how to implement a 4-bit loadable counter that
can count up (from 0-15 in decimal mode) as well as count down (15-0). In this example,
the counter resets to zero if rst is one. If ld is set, then the output (q3..q0) will be set to
the input (d3..d0). If cnten is set, then the counter is enabled and will count up/down
depending on the state of u_d (control pin). If cnten is not set the output will be held to
the last count.
3
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Table 1. 4-bit Loadable Counter Implementation
ABEL Source File (.ABL) CUPL Source File (.pld)
Module unicnt
Interface (d3..d0, clk, rst, cnten, ld, u_d -> q3..q0);
Title '4 bit counter with load, reset, count up, count down';
//Constants
X, C, Z = .X., .C., .Z. ;
Name counter;
Part no 00 ;
Date 6/30/02;
Revision 01;
Designer Engineer;
Company XYZ;
Assembly None;
Location San Jose;
Device virtual;
/*See Table 6 for description of each field in the header section*/
//Inputs
d3..d0 pin;
clk pin;
rst pin;
cnten pin;
ld pin;
u_d pin;
/* Input */
pin = [d3..0];
pin = clk;
pin = rst;
pin = cnten;
pin = ld;
pin = u_d;
//Output
q3..q0 pin is_type 'reg';
//Counter output, user can choose reg_d to select //D type
registers or reg_t for T-type Registers.
/* Output */
pin = [q3..0];
//Sets
data = [d3..d0]; //Data Set
count = [q3..q0]; //Counter Set
// Forming group of signals into a vector
MODE = [cnten,ld,u_d];
/* Data Set */
field data = [d3..0];
field count = [q3..0]; /* field is a way to group a set of signals */
/* Forming a group of signals into a vector */
field MODE = [cnten,ld,u_d];
// Selecting different modes base on vector values
// possible values are 0, 1, or don't cares
LOAD = (MODE == [X, 1, X]);
HOLD = (MODE == [0, 0, X]);
UP = (MODE == [1, 0, 1]);
DOWN = (MODE == [1, 0, 0]);
/* Selecting different modes based on vector values possible
values are 0, 1, or don't cares */
load = MODE:'b'X1X;
hold = MODE:'b'00X;
up = MODE:'b'101;
down = MODE:'b'100;
4 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Equations
when LOAD then count := data;
// Abel does things sequentially
else when UP then count := count + 1;
// Count up logic
else when DOWN then count := count - 1;
// Count down logic
else when HOLD then count := count;
// Hold otherwise
count.clk = clk; // Assign Flip-Flop clock pin
count.ar = rst; // Assign asynchronous reset for Flip-Flop
END unicnt //This specifies the end of the //equations section of
the module
/* The following will create a Moore FSM where the output will be
a function of the state */
SequenceD count { /* Explicitly choose D-FF, */
$REPEAT i = [0..15] /* This macro will expand from 0 to 15 */
Present 'h'{i} /* similar to case statement for each state */
If !load & up Next 'h'{(i+1)%16}; /* Logic for count up */
If !load & down Next 'h'{((i-1)+16)%16}; /* Logic for count down */
If !load & hold Next 'h'{i}; /* Logic for hold */
$REPEND}
APPEND count.d = load & data; /* This is when we want to load */
count.AR = rst; /* Asynchronous reset */
count.ck = clk;
ABEL Test Vectors CUPL Test Vectors
test_vectors ([clk, rst, cnten, ld, u_d, data] -> count)
[.c., 1, 0, 0, 0, 0] -> 0;
[.c., 0, 0, 1, 0, 8] ->8 ;
[.c., 0, 1, 0, 1, 8] -> 9;
[.c., 0, 1, 0, 1, 8] -> 10;
[.c., 0, 1, 0, 1, 8] -> 11;
[.c., 0, 1, 0, 1, 8] -> 12;
[.c., 0, 0, 1, 0, 15] -> 15;
[.c., 0, 1, 0, 0, 15] -> 14;
[.c., 0, 1, 0, 0, 15] -> 13;
[.c., 0, 1, 0, 0, 15] -> 12;
[.c., 1, 0, 0, 0, 15] -> 0;
// The abel test vectors can be included in the source code
file(.abl).
See "Converting an ABEL Simulation Input File to CUPL" on
page 5 for further information.
CUPL test vectors cannot be part of the Source file. A separate
(.si) file must be created as described on page 5.
See "Converting an ABEL Simulation Input File to CUPL" on
page 5 for further information.
Table 1. 4-bit Loadable Counter Implementation (Continued)
ABEL Source File (.ABL) CUPL Source File (.pld)
5
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Converting an ABEL
Simulation Input File
to CUPL
This section describes the features of ABEL and CUPL Simulation input files and the
process of converting an ABEL Simulation input file to a CUPL file. Test vectors must be
created for the simulator to function and they specify the expected functional operation
of a PLD by defining the outputs as a function of the inputs. Test vectors are also used
to do functional testing of a device once it has been programmed, to see if the device
functions as expected.
CUPL There are two tools within Atmel-WinCUPL that can be used to simulate the test vectors.
• WinSim® is a windows-based graphical tool used for creating and editing simulator
(.si) input files and for displaying the results of the simulation in the form of a
waveform. The CUPL simulator requires that a CUPL source file be successfully
compiled prior to running simulation. The CUPL compiler generates an intermediate
file (with extension .ABS) that is used by the simulator to run functional simulation.
• CSIM is a device-specific simulator and VSIM is a virtual simulator (virtual device)
that is text-based and inherently a DOS process. A test specification source file
(file name.si) is the input to CSIM/VSIM. The ATF15xx family of Atmel devices only
runs VSIM.
The source file may be created using a standard text editor in non-document mode. The
source specification file contains three major parts: header information and title block,
ORDER statement and a VECTORS statement.
A .si file must have the same header information as .pld (source) to ensure that the
proper files, including current revision level, are being compared against each other.
Therefore, first copy .pld to .si and then use a text editor to delete everything in .si,
except the header and title block.
ABEL There are two ways to specify test vectors. The most common method is to place test
vectors in the ABEL source file. If the user decides to use this method, the Project Navigator
(Atmel-Synario) will detect the presence of test vectors in the source file and
create a "dummy" test vector file. This file indicates to the system that the actual test
vectors are in the ABEL source file.
The other way to specify test vectors is to create a "real" test vector file by selecting the
"New" menu item in the Source menu and then choosing test vectors. Note that test vector
files have the .ABV file extension and must have the same name as the top-level
module. The user must use the Module and End statements exactly as he does when
creating an ABEL source file.
Table 2 shows comparative implementation of describing test vectors for ABEL simulation
(.ABV) and CUPL simulation (.SI) for the 4-bit counter.
6 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Table 2. Test Vector Description
Counter.abv Counter.si
Module unicnt
"Constants
X, C, Z = .X., .C., .Z.;
//Inputs
d3..d0 pin;
clk pin;
rst pin;
cnten pin;
ld pin;
u_d pin;
//Output
q3..q0 pin istype 'reg';
//Counter output,
//Sets
data = [d3..d0]; //Data Set
count = [q3..q0]; //Counter Set
test_vectors
([clk, rst, cnten, ld, u_d, data] -> count)
[.c., 1, 0, 0, 0, 0] -> 0;
[.c., 0, 0, 1,0, 8] ->8;
[.c., 0, 1, 0,1, 8] ->9;
[.c., 0, 1, 0,1, 8] ->10;
[.c., 0, 1, 0,1, 8] ->11;
[.c., 0, 1, 0,1, 8] ->12;
[.c., 0, 0, 1, 0, 15] -> 15;
[.c., 0, 1, 0, 0, 15] -> 14;
[.c., 0, 1, 0, 0, 15] -> 13;
[.c., 0, 1, 0, 0, 15] -> 12;
[.c., 1, 0, 0, 0, 15] -> 0;
End
Name counter;
Part no 00 ;
Date 6/30/02 ;
Revision 01 ;
Designer Engineer ;
Company XYZ ;
Assembly None ;
Location San Jose;
Device virtual ;
ORDER: clk, rst, cnten, ld, u_d, d3, d2, d1,
d0, q3, q2, q1, q0;
VECTORS:
c 1000 0000 LLLL
c 0010 1000 HLLL
c 0101 1000 HLLH
c 0101 1000 HLHL
c 0101 1000 HLHH
c 0101 1000 HHLL
c 0010 1111 HHHH
c 0100 1111 HHHL
c 0100 1111 HHLH
c 0100 1111 HHLL
c 1000 1111 LLLL
7
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Overview of Syntax
Differences between
ABEL and CUPL
The following section includes various tables that show the syntax differences between
the two languages pertaining to extensions, operators and keywords.
Reserved Identifiers
(Keywords)
Table 3. Syntax Differences
ABEL Keyword CUPL Keyword
ASYNCH_RESET None
CASE IF (in a CONDITION statement)
DECLARATIONS None
DEVICE PART NO
ELSE ELSE
END }
ENDCASE }
ENDWITH None
EQUATIONS None
EXTERNAL None
FLAG (OBSELETE) None
FUNCTIONAL_BLOCK None
FUSES FUSES
GOTO PRESENT, NEXT
IF IF (In a CONDITION statement)
IN None
INTERFACE None
ISTYPE Note 1
LIBRARY None
MACRO FUNCTION
MODULE None
NODE NODE/PINNODE
OPTIONS None
PIN PIN
PROPERTY PROPERTY (Note 2)
STATE PRESENT and $DEFINE
STATE_DIAGRAM SEQUENCE
STATE_REGISTER No equivalent but can be achieved with FIELD
SYNC_RESET None
TEST_VECTORS Generated .SI file
THEN NEXT
8 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Notes: 1. Instead of using "ISTYPE" in ABEL, one can use a suitable extension in CUPL.
Extensions such as .D (specify input to a D-type flip flop) can be used with any pin
name. The compiler will determine whether it is valid. The ISTYPE statement defines
attributes (characteristics) of signals (pins and nodes) in ABEL. Please refer to Table
4 for further details on ATTRIBUTES. The user should use signal attributes to remove
ambiguities in architecture-independent designs. Even when a device has been specified,
using attributes ensures that the design operates consistently if the device is
changed later.
2. Property statements are used specifically for the ATF1500A and the ATF15xx family
of devices to describe specific feature of the device that can be used by the Device
Fitter to generate the appropriate FITTER and Jedec files.
For Example:
Atmel-ABEL defines such as: ATMEL property 'DEDICATED_INPUT ON';
Atmel-CUPL defines such as: Property ATMEL {DEDICATED_INPUT ON};
TITLE NAME
TRACE None
TRUTH_TABLE TABLE
WHEN No equivalent but can be replaced by
CONDITION {}
WITH None
Table 4. Attributes Table
Signal Attributes Description
'buffer' No Inverter in Target Device
'collapse' Collapse (remove) this signal
'com' Combinational output
'dc' Unspecified logic is don't care
'invert' Inverter in Target Device
'keep' Do not collapse this signal from equations
'neg' Unspecified logic is 1
'pos' Unspecified logic is 0.
'retain' Do not minimize this output. Preserve redundant product
terms
'reg' Clocked Memory Element
'reg_d' D Flip-flop Clocked Memory Element
'reg_g' D Flip-flop Gated Clocked Memory Element
'reg_jk' JK Flip-flop Clocked Memory Element
'reg_sr' SR Flip-flop Clocked Memory Element
'reg_t' T Flip-flop Clocked Memory Element
'xor' XOR Gate in Target Device
Table 3. Syntax Differences (Continued)
ABEL Keyword CUPL Keyword
9
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Comments in ABEL and
CUPL
ABEL: Comments begin with a double quotation mark (") or double forward slash (//).
CUPL: Comments begin with /* and end with */.
Number Representation
in Different Bases
Header Information
Keywords
Logical Operator
Table 5. Number Representation in Different Bases
Base Name Base
Symbol
ABEL CUPL
Binary 2 ^b 'b'
Octal 8 ^o 'o'
Decimal 10 ^d 'd'
Hexadecimal 16 ^h 'h'
Table 6. Header Information Keywords
ABEL CUPL Description
Module Name Just a file name.
Title None
Used to give a title or description for the
module. (Optional)
None Part no
The part number for the particular PLD
design.
None Revision
Begin with 01 when first creating a file and
increment each time a file is altered.
None Date
Change to the current date each time a
source file is altered.
None Designer Specify the designer's name.
None Company Specify the company's name.
None Assembly
Give the assembly name or number of the PC
board.
None Location The abbreviation LOC can be used.
None Device
Used to set the default device type for the
compilation.
Table 7. Logical Operator
ABEL CUPL Description
! ! NOT (ones complement)
& & AND
# # OR
$ $ XOR(exclusiveOR)
! $ ! $ XNOR (exclusive NOR)
10 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Arithmetic Operators CUPL arithmetic operators can only be used inside $REPEAT and $MACRO blocks.
Relational Operators
Assignment Operators
Table 8. Arithmetic Operators
ABEL CUPL Description
- - Subtraction
+ + Addition
* * Multiplication
/ / Division
% % Modulus
<< None Shift left by bits
>> None Shift right by bits
Table 9. Relational Operators
ABEL CUPL Description
== None Equal
! = None Not equal
< None Less than
<= None Less than or equal
> None Greater than
>= None Greater than or equal
Table 10. Assignment Operators
ABEL CUPL Set Description
= = ON(1) Combinational or detailed assignment
: = = ON(1) Implied registered assignment
? = None DC(X) Combinational or detailed assignment
?:= None DC(X) Implied registered assignment
?:= None DC(X) Implied registered assignment
11
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Operator Priority
Dot Extension The dot extensions valid for pins or specific signals in CUPL as well as ABEL are listed
in Table 12.
Table 11. Operator Priority
ABEL CUPL Priority Description
- None 1 Negate
! ! 1 NOT
& & 2 AND
<< None 2 Shift left
>> None 2 Shift right
* * 2 Multiply
/ / 2 Unsigned division
% % 2 Modulus
+ + 3 Add
- - 3 Subtract
# # 3 OR
$ $ 3/4 XOR: exclusive OR
!$ None 3 XNOR: exclusive NOR
== None 4 Equal
!= None 4 Not equal
< None 4 Less than
<= None 4 Less than or equal
> None 4 Greater than
>= None 4 Greater than or equal
Table 12. Dot Extension
ABEL CUPL Description
.ACLR None Asynchronous clear
.ASET None Asynchronous set
.CLK .CK Clock input to an edge-triggered flip-flop
.CLR None Synchronous clear
.COM None
Combinational feedback normalized to the pin
value
.OE .OE Output enable
.PIN None Pin feedback
.SET None Synchronous set
.AP .AP Asynchronous preset
.AR .AR Asynchronous reset
12 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Notes: 1. The .CKMUX dot extension used in CUPL is specific to the Atmel ATV750B and
ATF750C devices. The .CKMUX extension is used to connect the clock input of a register
to the Synchronous clock pin. This is needed because some devices have a
multiplexer for connecting the clock to one set of pins.
2. .DFB and .DQ on CUPL are only used for D-type flip-flop. However, .FB and .Q in
ABEL can be used for any type of flip-flops such as D, T, JK, SR flip-flops.
.CE .CE Clock-enable input to a gated-clock flip-flop
.D .D Data input to a D-type flip-flop
.J .J J input to a JK-type flop-flop
.K .K K input to a JK-type flip-flop
.LD None Register load input
.LE None Latch-enable input to a latch
.LH .LE Latch-enable (high) to a latch
.PR .PR Register preset
.Q None Register feedback
.R .R R input to an SR-type flip-flop
.RE None Register reset
.S .S S input to an SR-type flip-flop
.SP .SP Synchronous register preset
.SR .SR Synchronous register reset
.T .T T input to a T-type (toggle) flip-flop
Note 1 .CKMUX Clock multiplexer selection
.FB (Note 2) .DFB D registered feedback path selection
.Q (Note 2) .DQ Q output of D-type flip-flop
None .INT Internal feedback path for registered macro cell
None .IO Pin feedback path selection
None .IOCK Clock for pin feedback register
None .IOD Pin feedback path through D register
None .IOL Pin feedback path through latch
None .L D input of transparent latch
None .LEMUX Latch enable multiplexer selection
None .LFB Latched feedback path selection
None .LQ Q output of transparent input latch
None .OEMUX Tri-state multiplexer selection
None .TFB T registered feedback path selection
Table 12. Dot Extension (Continued)
ABEL CUPL Description
13
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Extensions Applicable
for Atmel EPLD Devices
Table 13 lists specific extensions valid for Atmel EPLD devices.
Table 13. Valid Atmel EPLD Device Extensions
Atmel PLDs Valid Extensions
ATF16V8B/BQ/BQL OE, D
ATF16V8C/CZ
ATF20V8B/BQ/BQL
ATF20V8C/CQ/CQZ
ATF22V10C/CQ/CQZ OE, D, AR, SP
ATF22LV10C/CZ/CQZ
ATV750/L D, AR, CK, OE, SP, DFB, IO
ATV750B/BL D, T, AR, CK, CKMUZ, OE, SP, DFB, IO
ATF750C/CL/LVC/LVCL
ATF1500A/AL/ABV D, AR, CK, CE, OE, AP, IO, T, L, LE
ATV2500B/BL/BQ/BQL D, T, AR, CK, OE, SP, IO, CE
ATF2500C/CQ/CQL
ATF1502AS/ASL/ASV/ASVL D, T, S, R, OE, OEMUX, CK, CKMUX, AR,
DQ, LQ, IO
ATF1504AS/ASL/ASV/ASVL
ATF1508AS/ASL/ASV/ASVL
Printed on recycled paper.
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty
which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical
components in life support devices or systems.
Converting Xilinx Coolrunner Designs to Atmel ATF15xx low
Converting Xilinx Coolrunner Designs to Atmel ATF15xx low
power Family of CPLDs.
______________________________________________________________________________________
This application note shows a user the process of converting a discontinued Xilinx
Coolrunner(formerly Phillips family of CPLDs) Family of Programmable Logic Devices to Atmel
ATF15xx Family.
! Introduction
! Table of Devices with Atmel Equivalents
! Low Power benefits of Atmel ATF15xx Family of CPLDs
! Design Conversion Steps
! Conversion Issues
Introduction
In Q4 2000, Xilinx announced that production of a family of PLDs that had been acquired from
Phillips Semiconductor Corporation would be discontinued. The affected Xilinx products for which
Atmel equivalents are available include:
1. XCR3xxx/5xxx (3.3V & 5V XPLA Original)
2. XCR5xxxA/3xxxC/5xxxC (3.3V & 5V XPLA Enhanced)
3. XCR22LV10/22V10 (3.3V & 5V 22V10)
Atmel ATF15xxASL is a pin compatible replacement for the XCR5xxx (5V XPLA Original) and
XCR5xxxC (5V XPLA Enhanced). PCB boards do not require a re-spin for design migration to the
Atmel equivalents. Users can re-compile their ABEL, PHDL (Phillips version of ABEL), VHDL, or
Synario Schematic design files into ATF15xxASL using Atmel Software Design tools.
Atmel's ATF22LV10C/CQ/CQZ (3.3V version of the standard 22V10) and the
ATF22V10C/CQ/CQZ (5V version of the standard 22V10) are drop-in replacements for the
XCR22LV10 and XCR22V10 respectively. Since the 22V10s are JEDEC-compatible, no redesign
is required. Users can use the appropriate Atmel device type from the Third Party Programmer
menu(for e.g. Data-I/O Uni site, BP-1200) to program the Atmel ATF22V10C with the same
JEDEC file (programming file).
Table of Devices with Atmel Equivalents
Table 1 lists two alternative Atmel device for each Xilinx coolrunner device.
Use the "Speed match" column if power consumption is not an important design constraint.
However, devices in this column are all standard power devices, meaning that the Icc
consumption will be higher compared to their Coolrunner counterparts.
Use the low power Atmel equivalents, if Current consumption is an important Design criteria.
However there is a speed penalty. Table 2 is a representative snapshot of equivalent devices.
Please refer to an Atmel data sheet for detailed offering of speed grades. The same applies to the
Coolrunner devices
Xilinx P/N Atmel Cross (Speed Match)
Use this if Speed is an
important factor
Atmel Cross (Power Match)
Use this if Icc is an important
Design constraint
XCR22LV10-10PC28C ATF22LV10C-10JC ATF22LV10CQZ-30JC
XCR22V10-7PC28C ATF22V10C-7JC ATF22V10CQZ-20JC
XCR5032-7PC44C ATF1502AS-7JC44 ATF1502ASL-25JC44
XCR5032-7VQ44C ATF1502AS-7AC44 ATF1502ASL-25AC44
XCR5032C-7PC44C ATF1502AS-7JC44 ATF1502ASL-25JC44
XCR5032C-7VQ44C ATF1502AS-7AC44 ATF1502ASL-25AC44
XCR5064-7PC44C ATF1504AS-7JC44 ATF1504ASL-20JC44
XCR5064-7PC68C ATF1504AS-7JC68 ATF1504ASL-20JC68
XCR5064-7PC84C ATF1504AS-7JC84 ATF1504ASL-20JC84
XCR5064-7PQ100C ATF1504AS-7QC100 ATF1504ASL-20QC100
XCR5064-7VQ44C ATF1504AS-7AC44 ATF1504ASL-20AC44
XCR5064C-7PC44C ATF1504AS-7JC44 ATF1504ASL-20JC44
XCR5064C-7PQ100C ATF1504AS-7QC100 ATF1504ASL-20QC100
XCR5064C-7VQ44C ATF1504AS-7AC44 ATF1504ASL-20AC44
XCR5128-10PC84C ATF1508AS-10JC84 ATF1508ASL-20JC84
XCR5128-10PQ100C ATF1508AS-10QC100 ATF1508ASL-20QC100
XCR5128-10PQ160C ATF1508AS-10QC160 ATF1508ASL-20QC160
XCR5128-10VQ100C ATF1508AS-10AC100 ATF1508ASL-20AC100
XCR5128-7PC84C ATF1504AS-7JC84 ATF1508ASL-20JC84
XCR5128-7PQ100C ATF1508AS-7QC100 ATF1508AS-20QC100
XCR5128-7PQ160C ATF1508AS-7QC160 ATF1508ASL-20QC160
XCR5128-7VQ100C ATF1508AS-7AC100 ATF1508ASL-20AC100
XCR5128C-10VQ100C ATF1508AS-10AC100 ATF1508ASL-20AC100
XCR5128C-15VQ100C ATF1508AS-15AC100 ATF1508ASL-20AC100
XCR5128C-7VQ100C ATF1508AS-7AC100 ATF1508ASL-20AC100
XCR3032-12PC44C ATF1500ABV-12JC44 ATF1502ASV-20JC44
XCR3032-12VQ44C ATF1500ABV-12AC44 ATF1502ASV-20AC44
XCR3032A-10PC44C ATF1500ABV-12JC44 ATF1502ASV-20JC44
XCR3032A-10VQ44C ATF1500ABV-12AC44 ATF1502ASV-20AC44
XCR3032C-10PC44C ATF1500ABV-12JC44 ATF1502ASV-20JC44
XCR3032C-10VQ44C ATF1500ABV-12AC44 ATF1502ASV-20AC44
XCR3032C-12PC44C ATF1500ABV-12JC44 ATF1502ASV-20JC44
XCR3032C-12VQ44C ATF1500ABV-12AC44 ATF1502ASV-20AC44
The ATF1500ABV (non-ISP) is suggested to match the speed offering. The ATF1500ABV should be
considered if the Design is not using JTAG port pins for ISP.
XCR3064-12PC44C ATF1504ASV-15JC44 ATF1504ASVL-20JC44
XCR3064-12PQ100C ATF1504ASV-15QC100 ATF1504ASVL-20QC100
XCR3064-12VQ44C ATF1504ASV-15AC44 ATF1504ASVL-20AC44
XCR3064A-10PC44C ATF1504ASV-15JC44 ATF1504ASVL-20JC44
XCR3064A-10VQ100C ATF1504ASV-15AC100 ATF1504ASVL-20AI100
XCR3064A-10VQ44C ATF1504ASV-15AC44 ATF1504ASVL-20AC44
XCR3218-12PC84C ATF1508ASV-15JC84 ATF1508ASVL-20JC84
XCR3128-12PQ100C ATF1508ASV-15QC100 ATF1508ASVL-20QC100
XCR3128-12PQ160C ATF1508ASV-15QC160 ATF1508ASVL-20QC160
XCR3128-12VQ100C ATF1508ASV-15AC100 ATF1508ASVL-20AC100
XCR3128-12VQ100C ATF1508ASV-15AI100 ATF1508ASVL-20AC100
XCR3128-15PC84C ATF1508ASV-15JC84 ATF1508ASVL-20JI84
XCR3128-15PQ100C ATF1508ASV-15QC100 ATF1508ASVL-20QC100
XCR3128-15PQ160C ATF1508ASV-15QC160 ATF1508ASVL-20QC160
XCR3128-15VQ100C ATF1508ASV-15AC100 ATF1508ASVL-20AC100
XCR3128A-7VQ100C ATF1508ASV-15AC100 ATF1508ASVL-20AI100
Table 1
Low Power benefits of Atmel ATF15xx Family of CPLDs
The ATF15xx family includes the ATF1502AS, ATF1504AS and the ATF1508AS. The devices
have In-system programming (ISP) capability and are offered in low voltage/low power variations
and varying speed grades. The "L" mode (also called standby or sleep mode) refers to the low
power mode whereas "PD" refers to the use of specific Pins to power down the device. Standard
power devices are typically offered in faster speed grades and burn more power.
The current (Icc) consumption of a PLD in varying modes of operation is shown in Table 2.
Please refer to the individual device Data sheets for more information on power consumption. The
Atmel devices use approximately the same Icc when operating in the L mode when compared to
their Coolrunner counterparts.
Device Description "L" Mode PD Mode
ATF150xASL 5 V low power device 10µA (typ) Not applicable
ATF150xASVL 3.3 V low power device 5µA (typ) Not applicable
ATF150xASV 3.3 V standard power device Not applicable 750 µA
ATF150xAS 5 V standard power device Not applicable 1 mA
Note: x can be either 2, 4, 8, 16.
For example, the ATF1502 is offered as an ATF1502AS, ATF1502ASV, ATF1502ASL and ATF1502ASVL.
Table 2
DESIGN CONVERSION STEPS
Table 3 lists the Atmel conversion process using Atmel PLD Design tools.
Type of Design File
Source File
Extension
Xilinx
Design
Tools
Atmel Solution
ABEL .ABL Web fitter,
Synario
" Use Atmel-Synario to recompile Source ABEL file
" Download the latest fitters from the Atmel website
(SNPCH411.exe file)
" Refit the Design using the existing Pin assignments.
" Use Fitter property "Pin Preassignment = keep"
Note: User can also translate their ABEL Design to
CUPL or VHDL and use Atmel-WinCupl or Atmel
Prochip Designer Tool.
PHDL .PHD XPLA
(Phillips
tool)
" PHDL is similar to ABEL. Change the .PHD file
extension to .ABL and use the solution already
suggested for ABEL files
" Please see the section on Conversion issues for
more details on caveats of converting .PHD to .ABL
VHDL .VHD Web fitter,
Other EDA
vendors
Solution A:
" Use Prochip Designer Tool Environment to
resynthesize your Source design file.
" Use the EDIF (EDIF version 2.00) file with the Atmel
Device Fitter to fit your Design
Solution B:
" Use Atmel Synario tool with VHDL Synthesis option
to recompile your Source VHDL file and proceed
with the Synario tool flow.
Web fitter,
Synario
Solution A:
" Use Atmel-Synario to recompile Source Schematic
file
" Ensure that you have the latest fitters from the
Atmel website (download SNPCH411.exe file)
" Refit the Design using the existing Pin assignments.
" Use Fitter property "Pin Preassignment = keep"
Solution B:
" Use Prochip Designer to launch Design Explorer
and then redraw the schematic.
Schematic .SCH
Protel " Use Atmel Prochip Designer to launch Design
Explorer. Import the Source schematic and proceed
with the compile option.
" The resulting PLD file is first translated to CUPL
source and a .PLA and .EDIF file are created.
" Use the Device Fitter from the Prochip Design Flow
to use the .EDF file for fitting.
Note: Alternatively the Protel tool can also use the .PLA
file with the appropriate Device type to generate the
Fitter report file.
CUPL .PLD Protel/
Logical
Devices
Solution A:
" Recompile the source file using Atmel WinCupl.
" Use the Atmel Property {Preassign = keep} in the
source .PLD file.
Solution B:
" Use Atmel Prochip Designer to launch Design
Explorer. Import the Source .PLD file and proceed
with the compile option.
" The PLD file is compiled and a .PLA and .EDIF file
are created.
" Use the Device Fitter from the Prochip Design Flow
to use the .EDF file for fitting.
Note: Alternatively the Protel Design Explorer tool can
also use the .PLA file with the appropriate Device type
to generate the Fitter report file.
Table 3 Design Conversion Process
CONVERSION ISSUES
1. The Atmel ATF1504AS in 100-pin TQFP package is not entirely pin-compatible with the Xilinx
Cool-runner 64 macrocell device. The Coolrunner device pins 1 and 2 are connected to I/O
pins and pins 99, 100 are no-connects(NC) whereas in the Atmel device pins 99 and 100 are
I/Os and pins 1, 2 are NC pins. The workaround is to either use a Jumper or use the Board
trace to connect pins 99 and 100 to pins 1 and 2.
2. Working with .PHDL (formerly Phillips Hardware Description Language) files: The .X1
extension (applicable to XOR function in Coolrunner) is not supported in ABEL. Instead you
should rely on using an appropriate property in the source ABEL file to enable the Fitter to
use the XOR gate in the ATF15xx Macrocell for a particular Output pin.
Usage in ABEL:
PROPERTY ATMEL 'fitter option';
The fitter option for XOR Synthesis is:
-str xor_synthesis [on | OFF | = signal1, signal2,…]
Converting ABEL Design Files to CUPL
Converting ABEL Design Files to CUPL
This application note is intended to assist users in converting designs written in ABELHDL
language to CUPL. It also includes an example in ABEL and equivalent representation
in CUPL. Atmel® no longer offers ABEL compilers. Instead users are
encouraged to convert their designs to CUPL and use Atmel Design software tools
such as Atmel-WinCUPL™ or ProChip Designer™.
Background for ABEL and CUPL
ABEL-HDL and CUPL-HDL are behavioral design languages used to describe logic
circuits at a high level. ABEL evolved over the eighties and early nineties as a language
that was written to take advantage of the architectural features of an EPLD. As
late as 1995, Atmel continued to offer ABEL V5.1 (DOS-based program). This
required a Dongle (Key from Data I/O™ Corp. WA) to be plugged into the parallel port
of a PC. Subsequently, Atmel offered an EDA package called Atmel-Synario™ that
included a windows version of the ABEL compiler until the year 2000. Atmel-Synario
V4.11 was an OEM version specific for Atmel EPLDs and ABEL 6.5 (windows version)
was the last version of ABEL-HDL offered by Atmel as part of this package. Subsequently,
Data I/O spun off Synario as an EDA company and a little later Synario's
assets became a part of MINC Inc., another EDA Company. MINC then re-sold specific
tools from the Synario package to Xilinx®, Inc.
Logical Devices, Inc. developed CUPL and the structure of the language has not
changed much for the last two decades. Atmel offered a DOS version of CUPL until
the late nineties. The most recent DOS version of Atmel-WinCUPL shipped by Atmel
was Rev 4.8. Subsequently a windows version of CUPL (Rev 5.x) was offered and
called Atmel-WinCUPL.
ABEL/CUPL
Design File
Conversion
Application
Note
Rev. 3303A-PLD-08/02
2 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Compiler and Tool
Options
The CUPL compiler is available in Atmel-WinCUPL Version 5.2.16 software as well as
part of Atmel-ProChip Designer that uses a Third Party tool from Altium™ called Design
Explorer™ 99SE.
For simple designs, users are encouraged to use Atmel-WinCUPL which is a free tool
and available for download from Atmel's website.
The ABEL compiler (Rev. 6.5) used to compile the ABEL example was part of Atmel-
Synario Version 4.11 software, which is no longer offered.
Process of Conversion of
an ABEL Example File to
CUPL
The conversion is presented in the form of a Table (Table 1) and shows comparative
implementation in ABEL and CUPL. Users can first go through this example and then
refer to "Overview of Syntax Differences between ABEL and CUPL" on page 7 for Syntax
details. Simulation files are not required for every design unless users specifically
want to functionally generate a set of Test Vectors that can be applied on a Third Party
Programmer hardware. The process of writing Test vector files is listed in the section
titled "Converting an ABEL Simulation Input File to CUPL" on page 5.
Please note that in ABEL, it is possible to include Test vectors as part of the main
source file. The ABEL compiler will then extract the test vectors (.TMV) for simulation
purposes and to append the test vectors to the Jedec file.
Description of Example The following example in Table 1 shows how to implement a 4-bit loadable counter that
can count up (from 0-15 in decimal mode) as well as count down (15-0). In this example,
the counter resets to zero if rst is one. If ld is set, then the output (q3..q0) will be set to
the input (d3..d0). If cnten is set, then the counter is enabled and will count up/down
depending on the state of u_d (control pin). If cnten is not set the output will be held to
the last count.
3
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Table 1. 4-bit Loadable Counter Implementation
ABEL Source File (.ABL) CUPL Source File (.pld)
Module unicnt
Interface (d3..d0, clk, rst, cnten, ld, u_d -> q3..q0);
Title '4 bit counter with load, reset, count up, count down';
//Constants
X, C, Z = .X., .C., .Z. ;
Name counter;
Part no 00 ;
Date 6/30/02;
Revision 01;
Designer Engineer;
Company XYZ;
Assembly None;
Location San Jose;
Device virtual;
/*See Table 6 for description of each field in the header section*/
//Inputs
d3..d0 pin;
clk pin;
rst pin;
cnten pin;
ld pin;
u_d pin;
/* Input */
pin = [d3..0];
pin = clk;
pin = rst;
pin = cnten;
pin = ld;
pin = u_d;
//Output
q3..q0 pin is_type 'reg';
//Counter output, user can choose reg_d to select //D type
registers or reg_t for T-type Registers.
/* Output */
pin = [q3..0];
//Sets
data = [d3..d0]; //Data Set
count = [q3..q0]; //Counter Set
// Forming group of signals into a vector
MODE = [cnten,ld,u_d];
/* Data Set */
field data = [d3..0];
field count = [q3..0]; /* field is a way to group a set of signals */
/* Forming a group of signals into a vector */
field MODE = [cnten,ld,u_d];
// Selecting different modes base on vector values
// possible values are 0, 1, or don't cares
LOAD = (MODE == [X, 1, X]);
HOLD = (MODE == [0, 0, X]);
UP = (MODE == [1, 0, 1]);
DOWN = (MODE == [1, 0, 0]);
/* Selecting different modes based on vector values possible
values are 0, 1, or don't cares */
load = MODE:'b'X1X;
hold = MODE:'b'00X;
up = MODE:'b'101;
down = MODE:'b'100;
4 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Equations
when LOAD then count := data;
// Abel does things sequentially
else when UP then count := count + 1;
// Count up logic
else when DOWN then count := count - 1;
// Count down logic
else when HOLD then count := count;
// Hold otherwise
count.clk = clk; // Assign Flip-Flop clock pin
count.ar = rst; // Assign asynchronous reset for Flip-Flop
END unicnt //This specifies the end of the //equations section of
the module
/* The following will create a Moore FSM where the output will be
a function of the state */
SequenceD count { /* Explicitly choose D-FF, */
$REPEAT i = [0..15] /* This macro will expand from 0 to 15 */
Present 'h'{i} /* similar to case statement for each state */
If !load & up Next 'h'{(i+1)%16}; /* Logic for count up */
If !load & down Next 'h'{((i-1)+16)%16}; /* Logic for count down */
If !load & hold Next 'h'{i}; /* Logic for hold */
$REPEND}
APPEND count.d = load & data; /* This is when we want to load */
count.AR = rst; /* Asynchronous reset */
count.ck = clk;
ABEL Test Vectors CUPL Test Vectors
test_vectors ([clk, rst, cnten, ld, u_d, data] -> count)
[.c., 1, 0, 0, 0, 0] -> 0;
[.c., 0, 0, 1, 0, 8] ->8 ;
[.c., 0, 1, 0, 1, 8] -> 9;
[.c., 0, 1, 0, 1, 8] -> 10;
[.c., 0, 1, 0, 1, 8] -> 11;
[.c., 0, 1, 0, 1, 8] -> 12;
[.c., 0, 0, 1, 0, 15] -> 15;
[.c., 0, 1, 0, 0, 15] -> 14;
[.c., 0, 1, 0, 0, 15] -> 13;
[.c., 0, 1, 0, 0, 15] -> 12;
[.c., 1, 0, 0, 0, 15] -> 0;
// The abel test vectors can be included in the source code
file(.abl).
See "Converting an ABEL Simulation Input File to CUPL" on
page 5 for further information.
CUPL test vectors cannot be part of the Source file. A separate
(.si) file must be created as described on page 5.
See "Converting an ABEL Simulation Input File to CUPL" on
page 5 for further information.
Table 1. 4-bit Loadable Counter Implementation (Continued)
ABEL Source File (.ABL) CUPL Source File (.pld)
5
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Converting an ABEL
Simulation Input File
to CUPL
This section describes the features of ABEL and CUPL Simulation input files and the
process of converting an ABEL Simulation input file to a CUPL file. Test vectors must be
created for the simulator to function and they specify the expected functional operation
of a PLD by defining the outputs as a function of the inputs. Test vectors are also used
to do functional testing of a device once it has been programmed, to see if the device
functions as expected.
CUPL There are two tools within Atmel-WinCUPL that can be used to simulate the test vectors.
• WinSim® is a windows-based graphical tool used for creating and editing simulator
(.si) input files and for displaying the results of the simulation in the form of a
waveform. The CUPL simulator requires that a CUPL source file be successfully
compiled prior to running simulation. The CUPL compiler generates an intermediate
file (with extension .ABS) that is used by the simulator to run functional simulation.
• CSIM is a device-specific simulator and VSIM is a virtual simulator (virtual device)
that is text-based and inherently a DOS process. A test specification source file
(file name.si) is the input to CSIM/VSIM. The ATF15xx family of Atmel devices only
runs VSIM.
The source file may be created using a standard text editor in non-document mode. The
source specification file contains three major parts: header information and title block,
ORDER statement and a VECTORS statement.
A .si file must have the same header information as .pld (source) to ensure that the
proper files, including current revision level, are being compared against each other.
Therefore, first copy .pld to .si and then use a text editor to delete everything in .si,
except the header and title block.
ABEL There are two ways to specify test vectors. The most common method is to place test
vectors in the ABEL source file. If the user decides to use this method, the Project Navigator
(Atmel-Synario) will detect the presence of test vectors in the source file and
create a "dummy" test vector file. This file indicates to the system that the actual test
vectors are in the ABEL source file.
The other way to specify test vectors is to create a "real" test vector file by selecting the
"New" menu item in the Source menu and then choosing test vectors. Note that test vector
files have the .ABV file extension and must have the same name as the top-level
module. The user must use the Module and End statements exactly as he does when
creating an ABEL source file.
Table 2 shows comparative implementation of describing test vectors for ABEL simulation
(.ABV) and CUPL simulation (.SI) for the 4-bit counter.
6 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Table 2. Test Vector Description
Counter.abv Counter.si
Module unicnt
"Constants
X, C, Z = .X., .C., .Z.;
//Inputs
d3..d0 pin;
clk pin;
rst pin;
cnten pin;
ld pin;
u_d pin;
//Output
q3..q0 pin istype 'reg';
//Counter output,
//Sets
data = [d3..d0]; //Data Set
count = [q3..q0]; //Counter Set
test_vectors
([clk, rst, cnten, ld, u_d, data] -> count)
[.c., 1, 0, 0, 0, 0] -> 0;
[.c., 0, 0, 1,0, 8] ->8;
[.c., 0, 1, 0,1, 8] ->9;
[.c., 0, 1, 0,1, 8] ->10;
[.c., 0, 1, 0,1, 8] ->11;
[.c., 0, 1, 0,1, 8] ->12;
[.c., 0, 0, 1, 0, 15] -> 15;
[.c., 0, 1, 0, 0, 15] -> 14;
[.c., 0, 1, 0, 0, 15] -> 13;
[.c., 0, 1, 0, 0, 15] -> 12;
[.c., 1, 0, 0, 0, 15] -> 0;
End
Name counter;
Part no 00 ;
Date 6/30/02 ;
Revision 01 ;
Designer Engineer ;
Company XYZ ;
Assembly None ;
Location San Jose;
Device virtual ;
ORDER: clk, rst, cnten, ld, u_d, d3, d2, d1,
d0, q3, q2, q1, q0;
VECTORS:
c 1000 0000 LLLL
c 0010 1000 HLLL
c 0101 1000 HLLH
c 0101 1000 HLHL
c 0101 1000 HLHH
c 0101 1000 HHLL
c 0010 1111 HHHH
c 0100 1111 HHHL
c 0100 1111 HHLH
c 0100 1111 HHLL
c 1000 1111 LLLL
7
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Overview of Syntax
Differences between
ABEL and CUPL
The following section includes various tables that show the syntax differences between
the two languages pertaining to extensions, operators and keywords.
Reserved Identifiers
(Keywords)
Table 3. Syntax Differences
ABEL Keyword CUPL Keyword
ASYNCH_RESET None
CASE IF (in a CONDITION statement)
DECLARATIONS None
DEVICE PART NO
ELSE ELSE
END }
ENDCASE }
ENDWITH None
EQUATIONS None
EXTERNAL None
FLAG (OBSELETE) None
FUNCTIONAL_BLOCK None
FUSES FUSES
GOTO PRESENT, NEXT
IF IF (In a CONDITION statement)
IN None
INTERFACE None
ISTYPE Note 1
LIBRARY None
MACRO FUNCTION
MODULE None
NODE NODE/PINNODE
OPTIONS None
PIN PIN
PROPERTY PROPERTY (Note 2)
STATE PRESENT and $DEFINE
STATE_DIAGRAM SEQUENCE
STATE_REGISTER No equivalent but can be achieved with FIELD
SYNC_RESET None
TEST_VECTORS Generated .SI file
THEN NEXT
8 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Notes: 1. Instead of using "ISTYPE" in ABEL, one can use a suitable extension in CUPL.
Extensions such as .D (specify input to a D-type flip flop) can be used with any pin
name. The compiler will determine whether it is valid. The ISTYPE statement defines
attributes (characteristics) of signals (pins and nodes) in ABEL. Please refer to Table
4 for further details on ATTRIBUTES. The user should use signal attributes to remove
ambiguities in architecture-independent designs. Even when a device has been specified,
using attributes ensures that the design operates consistently if the device is
changed later.
2. Property statements are used specifically for the ATF1500A and the ATF15xx family
of devices to describe specific feature of the device that can be used by the Device
Fitter to generate the appropriate FITTER and Jedec files.
For Example:
Atmel-ABEL defines such as: ATMEL property 'DEDICATED_INPUT ON';
Atmel-CUPL defines such as: Property ATMEL {DEDICATED_INPUT ON};
TITLE NAME
TRACE None
TRUTH_TABLE TABLE
WHEN No equivalent but can be replaced by
CONDITION {}
WITH None
Table 4. Attributes Table
Signal Attributes Description
'buffer' No Inverter in Target Device
'collapse' Collapse (remove) this signal
'com' Combinational output
'dc' Unspecified logic is don't care
'invert' Inverter in Target Device
'keep' Do not collapse this signal from equations
'neg' Unspecified logic is 1
'pos' Unspecified logic is 0.
'retain' Do not minimize this output. Preserve redundant product
terms
'reg' Clocked Memory Element
'reg_d' D Flip-flop Clocked Memory Element
'reg_g' D Flip-flop Gated Clocked Memory Element
'reg_jk' JK Flip-flop Clocked Memory Element
'reg_sr' SR Flip-flop Clocked Memory Element
'reg_t' T Flip-flop Clocked Memory Element
'xor' XOR Gate in Target Device
Table 3. Syntax Differences (Continued)
ABEL Keyword CUPL Keyword
9
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Comments in ABEL and
CUPL
ABEL: Comments begin with a double quotation mark (") or double forward slash (//).
CUPL: Comments begin with /* and end with */.
Number Representation
in Different Bases
Header Information
Keywords
Logical Operator
Table 5. Number Representation in Different Bases
Base Name Base
Symbol
ABEL CUPL
Binary 2 ^b 'b'
Octal 8 ^o 'o'
Decimal 10 ^d 'd'
Hexadecimal 16 ^h 'h'
Table 6. Header Information Keywords
ABEL CUPL Description
Module Name Just a file name.
Title None
Used to give a title or description for the
module. (Optional)
None Part no
The part number for the particular PLD
design.
None Revision
Begin with 01 when first creating a file and
increment each time a file is altered.
None Date
Change to the current date each time a
source file is altered.
None Designer Specify the designer's name.
None Company Specify the company's name.
None Assembly
Give the assembly name or number of the PC
board.
None Location The abbreviation LOC can be used.
None Device
Used to set the default device type for the
compilation.
Table 7. Logical Operator
ABEL CUPL Description
! ! NOT (ones complement)
& & AND
# # OR
$ $ XOR(exclusiveOR)
! $ ! $ XNOR (exclusive NOR)
10 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Arithmetic Operators CUPL arithmetic operators can only be used inside $REPEAT and $MACRO blocks.
Relational Operators
Assignment Operators
Table 8. Arithmetic Operators
ABEL CUPL Description
- - Subtraction
+ + Addition
* * Multiplication
/ / Division
% % Modulus
<< None Shift left by bits
>> None Shift right by bits
Table 9. Relational Operators
ABEL CUPL Description
== None Equal
! = None Not equal
< None Less than
<= None Less than or equal
> None Greater than
>= None Greater than or equal
Table 10. Assignment Operators
ABEL CUPL Set Description
= = ON(1) Combinational or detailed assignment
: = = ON(1) Implied registered assignment
? = None DC(X) Combinational or detailed assignment
?:= None DC(X) Implied registered assignment
?:= None DC(X) Implied registered assignment
11
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Operator Priority
Dot Extension The dot extensions valid for pins or specific signals in CUPL as well as ABEL are listed
in Table 12.
Table 11. Operator Priority
ABEL CUPL Priority Description
- None 1 Negate
! ! 1 NOT
& & 2 AND
<< None 2 Shift left
>> None 2 Shift right
* * 2 Multiply
/ / 2 Unsigned division
% % 2 Modulus
+ + 3 Add
- - 3 Subtract
# # 3 OR
$ $ 3/4 XOR: exclusive OR
!$ None 3 XNOR: exclusive NOR
== None 4 Equal
!= None 4 Not equal
< None 4 Less than
<= None 4 Less than or equal
> None 4 Greater than
>= None 4 Greater than or equal
Table 12. Dot Extension
ABEL CUPL Description
.ACLR None Asynchronous clear
.ASET None Asynchronous set
.CLK .CK Clock input to an edge-triggered flip-flop
.CLR None Synchronous clear
.COM None
Combinational feedback normalized to the pin
value
.OE .OE Output enable
.PIN None Pin feedback
.SET None Synchronous set
.AP .AP Asynchronous preset
.AR .AR Asynchronous reset
12 ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Notes: 1. The .CKMUX dot extension used in CUPL is specific to the Atmel ATV750B and
ATF750C devices. The .CKMUX extension is used to connect the clock input of a register
to the Synchronous clock pin. This is needed because some devices have a
multiplexer for connecting the clock to one set of pins.
2. .DFB and .DQ on CUPL are only used for D-type flip-flop. However, .FB and .Q in
ABEL can be used for any type of flip-flops such as D, T, JK, SR flip-flops.
.CE .CE Clock-enable input to a gated-clock flip-flop
.D .D Data input to a D-type flip-flop
.J .J J input to a JK-type flop-flop
.K .K K input to a JK-type flip-flop
.LD None Register load input
.LE None Latch-enable input to a latch
.LH .LE Latch-enable (high) to a latch
.PR .PR Register preset
.Q None Register feedback
.R .R R input to an SR-type flip-flop
.RE None Register reset
.S .S S input to an SR-type flip-flop
.SP .SP Synchronous register preset
.SR .SR Synchronous register reset
.T .T T input to a T-type (toggle) flip-flop
Note 1 .CKMUX Clock multiplexer selection
.FB (Note 2) .DFB D registered feedback path selection
.Q (Note 2) .DQ Q output of D-type flip-flop
None .INT Internal feedback path for registered macro cell
None .IO Pin feedback path selection
None .IOCK Clock for pin feedback register
None .IOD Pin feedback path through D register
None .IOL Pin feedback path through latch
None .L D input of transparent latch
None .LEMUX Latch enable multiplexer selection
None .LFB Latched feedback path selection
None .LQ Q output of transparent input latch
None .OEMUX Tri-state multiplexer selection
None .TFB T registered feedback path selection
Table 12. Dot Extension (Continued)
ABEL CUPL Description
13
ABEL/CUPL Design File Conversion
3303A-PLD-08/02
Extensions Applicable
for Atmel EPLD Devices
Table 13 lists specific extensions valid for Atmel EPLD devices.
Table 13. Valid Atmel EPLD Device Extensions
Atmel PLDs Valid Extensions
ATF16V8B/BQ/BQL OE, D
ATF16V8C/CZ
ATF20V8B/BQ/BQL
ATF20V8C/CQ/CQZ
ATF22V10C/CQ/CQZ OE, D, AR, SP
ATF22LV10C/CZ/CQZ
ATV750/L D, AR, CK, OE, SP, DFB, IO
ATV750B/BL D, T, AR, CK, CKMUZ, OE, SP, DFB, IO
ATF750C/CL/LVC/LVCL
ATF1500A/AL/ABV D, AR, CK, CE, OE, AP, IO, T, L, LE
ATV2500B/BL/BQ/BQL D, T, AR, CK, OE, SP, IO, CE
ATF2500C/CQ/CQL
ATF1502AS/ASL/ASV/ASVL D, T, S, R, OE, OEMUX, CK, CKMUX, AR,
DQ, LQ, IO
ATF1504AS/ASL/ASV/ASVL
ATF1508AS/ASL/ASV/ASVL
Printed on recycled paper.
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty
which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical
components in life support devices or systems.
Atmel Headquarters Atmel Operations
Corporate Headquarters
Tutorial: CPLD Design Flow Tutorial
Tutorial: CPLD Design Flow Tutorial
This tutorial will guide you through a complete design cycle for the Atmel ATF15xx CPLD with Logic Doubling
architecture. It will step-by-step go through each phase of the design cycle from design entry, logic synthesis, device
fitting, in-system programming, and finally verifying the design on the Atmel CPLD Development/Programming
Board.
Note: To complete this tutorial, ProChip Designer V4.0 or later and Atmel-ISP Software (ATMISP) V4.0 or
later are required.
I : Create a Project using ProChip Designer's New Project Wizard
II : Add a Design File
III : Compile the Design
IV : Fit the Synthesized Design File
V : Program and Verify Design
I. Create a Project using the "New Project Wizard"
I. Create a Project using the "New Project Wizard"
Before starting the design process, a Project File must be created within ProChip Designer. ProChip Designer's
New Project Wizard provides a very easy way to create a new Project File.
1. Click on the START …. PROGRAMS …. PROCHIP Icon to launch ProChip Designer.
Or double-click on the PROCHIP icon on the desktop.
(1) Click to
launch
ProChip
Designer
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 2
2. Click on PROJECT .... NEW or double-click on the NEW PROJECT shortcut button to launch the New
Project Wizard.
3. Click on the NEXT button to start the project file creation process.
4. Click on the BROWSE button to open the browser window.
5. Use C:\PROCHIP\DESIGNS\CUPL as the directory of the project.
6. Enter DEV_KIT.APJ as the project file name. The extension of a project file must be .APJ.
Note: The name and directory of the design project is specified in this window. All design, simulation, and
other project files must be placed in this project directory.
(2) Click to
create new
project
(3) Click NEXT
to start
(5) Select the
project directory
(6) Enter the project
file name
(4) Click on
BROWSE
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 3
7. Choose [ATF1508AS-10JC84] as the target device type for the project. Also review the Filters that allow for
selection of a specific Speed Grade or Package Type.
8. Select CUPL - ALTIUM as the software tool for this design flow.
With ProChip Designer V4.0 and later, the five possible design flows and their corresponding design entry types
supported are listed in the table below:
Design Flow Design Entry Type
CUPL - Altium CUPL design entry through Altium Protel 99SE
Verilog - Mentor Graphics* Verilog design entry through Mentor Graphics LeonardoSpectrum
VHDL - Altium VHDL design entry through the Altium PeakFPGA
VHDL - Mentor Graphics* VHDL design entry through Mentor Graphics LeonardoSpectrum
Schematic - Altium Schematic design entry through Altium Protel 99SE
* Requires Mentor Graphics LeonardoSpectrum software with Atmel CPLD support.
(7) Select the
device type
(8) Select the
design flow
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 4
9. Select DONE WITH PARTS so that there will be only one device in this project.
On the other hand, users can select ADD MORE PARTS to include more parts to the current Project Directory.
10. Click the FINISH button to finish the New Project Wizard and the project creation process.
This closes the New Project Wizard and opens the ProChip Designer window. The Sources in the project are
shown in the Left window.
(9) Select "Done
with parts"
(10) Click FINISH to
end New
Project Wizard
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 5
11. Click on the Device Icon [ATF1508AS-10JC84] to view the Design Flow window.
Project Sources Window Information Dialog Box
Message Window (11) Click on the Device Icon
Design Flow Window Project File Window
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 6
II. Add a Design File
II. Add a Design File
Once the Project File is created, the next step is to add the design source file(s) into your project. For this tutorial, a
single CUPL design file will be added into the project.
1. Click on the ADD/EDIT button from Source Manager to open the Source Manager Window. You can view the
Source Manager Help File by clicking on the Help button within the Source Manager Window to view the
description for the different processes.
2. In the Source Manager Window, click on the ADD button to add a CUPL design file to the project.
3. In the File Manager Window, select LOGIC_D8.PLD from the C:\PROCHIP\DESIGNS\CUPL directory as the
source design file for this project.
This "LOGIC_D8.PLD" is a CUPL design that uses the eight 8-segment LED displays and the built-in oscillator on
the Atmel CPLD Development/Programmer Board to generate a scrolling message that displays the words "logic
doubling" on the LEDs. The GOE push-button switch is used to control the direction that the message scrolls in
(left or right). The GCLR push-button switch is used to reset the counter registers. When the GCLR push-button
switch is depressed, the message will stop scrolling. This CUPL design can be compiled using either the ProChip
Designer or the Atmel-WinCUPL software.
The first section of the LOGIC_D8.PLD as shown below pre-defines which segments of the LED should be asserted
in order to display the desired letter or number. For example, to display the upper case letter "C", segments A, D, E,
and F need to be set to low (active low) and the remaining segments need to be set to high.
$define Font0 'b'1000000 /* = ( _f_e_d_c_b_a ); 0 */
$define Font1 'b'1111001 /* = ( _c_b ); 1 */
:
$define FontA 'b'0001000 /* = (_g_f_e _c_b_a ); A */
(1) Click
Add/Edit to
open Source
Manger
Window
(2) Click Add
to add
design file
(3) Select
CUPL
source file
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 7
The next section of this CPLD design as shown below illustrates how to declare and assign pin numbers in the
CUPL language to the input and output signals. The input and output pin assignments are assigned according to the
connections between the CPLD and the eight 8-segment LED's as shown in the connection tables (Table 2-1 to 2-8)
in Section 2.
/* Inputs */
pin 1 = GCLR; /* Global Clear input */
pin 83 = MCLK; /* Global Clock input */
pin 84 = GOE; /* GOE1 button used as direction control */
/* Outputs */
/* DSP1 */
pin 49 = LED1A; /* LED1 segment A */
pin 46 = LED1B; /* LED1 segment B */
pin 48 = LED1C; /* LED1 segment C */
pin 50 = LED1D; /* LED1 segment D */
pin 52 = LED1E; /* LED1 segment E */
pin 51 = LED1F; /* LED1 segment F */
pin 54 = LED1G; /* LED1 segment G */
Next the buried signals for the counter and state machine are declared as Pin node's as shown below. The
feedback and/or the foldback paths available in each macrocell implement these buried signals. For the listing of the
pin node numbers, please refer to the "ATF15xx Device Help" section of the ProChip Designer Help File.
pin node [618,634,650,687]= [CA20..CA17];
pin node = [CA16..CA0];
pin node = [SM7..SM0];
After assigning the input, output and buried signals, the related signals (e.g. the LED segments and buried counter)
are grouped together as shown below to make the design source code more readable and manageable. In CUPL, the
"Field" declaration can be used to group a specific set of signals.
Field DSP1 = [LED1G,LED1F,LED1E,LED1D,LED1C,LED1B,LED1A];
Field DSP2 = [LED2G,LED2F,LED2E,LED2D,LED2C,LED2B,LED2A];
:
Field CNT_A = [CA20..CA0];
Field SM = [SM7..SM0];
Next a 21-bit buried up-counter implemented using D-type Flip-flops is shown below and it is used to divide the
2.0MHz clock into a 0.954Hz (2MHz ¸ 221 = 0.954Hz) signal that can be used to display the text messages. The last
bit of this counter is used as the clock for the state machine that controls the display sequence of the messages on the
LEDs.
CA0.d = !CA0;
CA1.d = CA0 $ CA1;
:
CA7.d = (CA6 & CA5 & CA4 & CA3 & CA2 & CA1 & CA0) $ CA7;
:
CNT_A.ck = MCLK;
CNT_A.ar = !GCLR;
The next section of this PLD design is a state machine with 15 states to control the display sequence of the text
messages on the LEDs. The GOE push-button switch on the CPLD Development/Programmer Board controls the
flow of this state machine. When this switch is in the "up" position, the state machine will go from RESET to State-
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 8
0 to State-1 to State-2 and so on until it reaches State-14 and then it will go back to State-0. On the other hand, if
the GOE switch is in the "down" position, the state machine will go in the opposite direction (e.g. State-14 to
State13 .. etc).
SM.ck = COUNTER_1;
sequence SM
{
present RESET
next S0;
present S0
if SM_DIR next S1;
if !SM_DIR next S14;
:
present S14
if SM_DIR next S0;
if !SM_DIR next S13;
}
Finally, the last section of the PLD design will assign the appropriate letters or numbers to the eight 8-segment
LEDs to be displayed during the different states of the state machine. You can easily change the letters/numbers to
be displayed by changing this section of the code to the appropriate pre-defined letters/numbers.
LED1 = FontBK & SM:[RESET]
# FontBK & SM:[S0]
# FontLl & SM:[S1]
# FontLo & SM:[S2]
# FontLg & SM:[S3]
# FontLi & SM:[S4]
# FontLc & SM:[S5]
# FontBK & SM:[S6]
# FontLd & SM:[S7]
# FontLo & SM:[S8]
# FontLu & SM:[S9]
# FontLb & SM:[S10]
# FontLl & SM:[S11]
# FontLi & SM:[S12]
# FontLn & SM:[S13]
# FontLg & SM:[S14];
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 9
III. Compile the CUPL Design
III. Compile the CUPL Design
In this part of the tutorial, the CUPL design will be compiled through the Logic Synthesis process into a set of
optimized/minimized logic equations.
1. Click on the CUPL - DESIGN EX. button in the Design Flow Window to open the Logic Synthesis Window.
2. Make sure all of the options in the Optimization section are unchecked.
3. Make sure the Minimization setting is set to QUICK.
4. Click on the COMPILE button to start the CUPL compile process.
You can click on the SET DEFAULTS button and it will automatically specify the Synthesis tool in the Tool Text
box.
If you click on the CUPL Tab, it shows the various Synthesis options. You may refer to the HELP file for further
description.
(1) Open Logic
Synthesis
Window
(4) Start the
Compile
process
(2) Make sure these
options are
unchecked
(3) Set to
Quick
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 10
IV. Fit the Synthesized Design File
IV. Fit the Synthesized Design File
In Section 3.3, the Logic Synthesis portion of the CPLD Design Flow was completed. On successful compilation,
the CUPL compiler tool produces a PLA output file (with extension .pla). A PLA file contains the net list of the
optimized and minimized logic equations. We now need to map this net list into a specific Atmel PLD architecture
using the ATMEL FITTER.
1. You can now proceed to the Device Fitter portion of the Design Flow by clicking on the ATMEL FITTER
button.
You can either use the Default options or specify Fitter properties. ProChip Designer will automatically select the
PLA file associated to the current design project and the tool type. In this example, since our target device is an
ATF1508AS, and we will select the fit1508.exe device fitter.
The fitter creates the important JEDEC and FIT REPORT output files. They contain the data for programming the
Device (using In-System Programming or on a third party device programmer) and the pin assignments required for
board layout respectively.
Please review the Global Device Parameters and Pin/Node Options as well. The Help Files also show the Device
Pin_Node lists for each of the ATMEL CPLDs.
2. Make sure the JTAG box is checked. This enables the JTAG port for ISP programming.
3. Make sure the PIN FIT CONTROL setting is set to KEEP. This will ensure that the pin assignments in the PLD
file will be kept during the Place-and-Route process.
4. Make sure the Logic Double setting is set to ALWAYS. This enables the fitter to use the ATF15xx Logic
Doubling features at the beginning of the first fitter pass.
5. When all the fitter options are set, click on the RUN FITTER button to fit the design.
(1) Open the Atmel
Fitter Window
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 11
The Fitter Report (.FIT) File generated for this design is shown below.
Atmel ATF1508AS Fitter Version 1.8.7.1 ,running Fri Jun 14 15:15:23 2002
:
Logic Array Block Logic Cells I/O Pins Fold backs TotalPT FanIN
Cascades
A: LC1 - LC16 16/16(100%) 8/16(50%) 5/16(31%) 46/80(57%) (19) 0
B: LC17 - LC32 16/16(100%) 8/16(50%) 3/16(18%) 51/80(63%) (38) 0
C: LC33 - LC48 16/16(100%) 8/16(50%) 2/16(12%) 48/80(60%) (38) 0
D: LC49 - LC64 16/16(100%) 6/16(37%) 2/16(12%) 40/80(50%) (38) 0
E: LC65 - LC80 16/16(100%) 6/16(37%) 6/16(37%) 55/80(68%) (32) 0
F: LC81 - LC96 16/16(100%) 8/16(50%) 2/16(12%) 47/80(58%) (38) 0
G: LC97 - LC112 16/16(100%) 8/16(50%) 3/16(18%) 43/80(53%) (25) 0
H: LC113- LC128 16/16(100%) 8/16(50%) 2/16(12%) 42/80(52%) (34)
0
Total dedicated input used: 3/4 (75%)
Total I/O pins used 60/64 (93%)
Total Logic cells used 128/128 (100%)
Total Flip-Flop used 31/128 (24%)
Total Foldback logic used 25/128 (19%)
Total Nodes+FB/MCells 153/128 (119%)
Total cascade used 0
Total input pins 7
Total output pins 56
Total Pts 372
:
(3) Set the Pin
Fit Control
setting to
KEEP
(5) Start the
fitting process
(2) Check the
JTAG box
(4) Set Logic Double
to "always"
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 12
The ATF15xx Family devices Logic Doubling features provide extra I/O connectivity and logic re usability. Some
of the Logic Doubling features available in the ATF15xx family of CPLDs are:
§ Bury either Register or Combinatorial signal while using the other for output
§ Dual independent feedback allows multiple latch functions per macrocell
§ 5 product terms per macrocell, expandable to 40 per macrocell with cascade logic, plus 15 more with foldback
logic
§ D/T/Latch configurable flip-flops plus transparent latches
§ Global and/or per macrocell Output Enable
§ Single level Switch Matrix
§ Up to 40 inputs per Logic Block
In the LOGIC_D8.PLD example given in this tutorial, some of the Logic Blocks have 37 signal inputs (Fan-In's) as
shown in the .FIT file. The availability of wide Fan-In's to the Logic Blocks is one of the many Logic Doubling
features. This feature improves the possibility of routing all the necessary signals from the Global Bus to the Logic
Blocks.
In addition, macrocells 37 and 59 of the ATF1508 are able to implement both combinatorial outputs (LED1G and
LED8D) and buried registered signals (CA0 and RST) within the same macrocells. This is shown in the Resource
Usage section of the .FIT file.
For more examples of design techniques that utilize the Logic Doubling features of the ATF15xx Family, refer to
Atmel's Logic Doubling White Paper and Reference Designs available on the Atmel website. These examples show
how to apply Logic Doubling techniques to new product designs, and obtain the benefits of more features in a
smaller, and possibly less expensive chip, or spare logic resources for future revisions and reduce the risk of PCB respin.
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 13
V. Program and Verify Design
V. Program and Verify Design
In this step of the tutorial, you will program an ATF1508AS 84-pin PLCC device on the Atmel CPLD
Development/Programmer Board through ISP and then verify the design by observing the text messages displayed on the eight 8-segment LED displays of the CPLD Development/Programmer Board.
You will need to follow the steps below to setup the ATMISP software in order to program the ATF1508AS 84-pin PLCC on the CPLD Development/Programmer Board.
1. To create a new chain file, the ATMISP Software first needs to be launched either through the PROGRAM
CHIP button in the ProChip Designer window, the ATMISP desktop icon or the Start … Programs .. Atmel ISP
menu.
Note: If ATMISP is launched through ProChip Designer, then the appropriate chain (.CHN) file will be
automatically created by ProChip Designer. Therefore, Steps 2 to 6 can be skipped.
2. To create a new chain file, select the New command under the File menu or click on the New shortcut button.
3. The first piece of information that the software asks for when creating a new chain is the number of devices in the JTAG chain. Therefore, enter 1 and then click OK since you will be programming a 1-device JTAG chain.
(1) Launch ATMISP
(2) Create new chain file
(3) Enter the number of device
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 14
4. Next you will need to specify the properties of each JTAG device in the Device Properties window. First, you
will need to select the target device type of the first device in the JTAG chain. For this tutorial, please select
ATF1508AS as the target device type.
5. In the JTAG Instruction field, you can specify which JTAG instruction to be executed on this device in the
chain. Please select Program/Verify to program and verify the ATF1508AS.
6. The next step is to specify the JEDEC file to be programmed into the target device in the JEDEC File field.
Click on the Browse button, change the directory to [..\PROCHIP\DESIGNS\CUPL"] and then select
LOGIC_D.JED as the JEDEC file. Click OK to close the JTAG Device Properties window when all properties
are specified. The next step requires you to setup the Atmel CPLD Development/Programmer Board to program the ATF1508AS through ISP.
7. Connect the 25-DB side of the Atmel-ISP Cable to the PC's parallel port and the 10-pin header side to the
Atmel-ISP Cable to the Atmel CPLD Development Board as shown Figure 2-5.
8. Connect a 9V AC/DC power adapter to the power connector (JPower) of the Atmel CPLD
Development/Programmer Board.
9. Set the 5V/3.3V jumper to 5V to set the system Vcc to 5V.
10. Set the JPCLK jumper to GCLK1 so that the output of the crystal oscillator will go to Pin 83 of the
ATF1508AS.
11. Connect the 84-pin PLCC Socket Adapter Board onto the main Development/Programmer Board.
Note: If a device in a different package type is to be programmed, then the appropriate Socket Adapter Board
must be used.
12. Switch the Power Switch to the ON position.
13. Select which LPT port is being used for ISP in the Port Setting field. LPT 1 is the default port.
14. Select the ISP download cable type in the Cable Types field. The default cable type is the Atmel ISP Cable but it can be changed to the Altera Byte blaster cable if you are using the Byte blaster cable.
(4) Specify target device type
(5) Specify JTAG instruction
(6) Select JEDEC file
Atmel CPLD Development Kit - CPLD Design Flow Tutorial P. 15
Now both your software and hardware are setup for ISP programming, and you can execute the
PROGRAM/VERIFY instruction to program the ATF1508AS on the Atmel CPLD Development/Programmer
Board.
15. Click on the RUN button in the ATMISP main window to execute the JTAG instruction to program the
ATF1508AS on the CPLD Development/Programmer Board.
After the successfully programming the ATF1508AS with the LOGIC_D8.JED file, the eight 8-segment LED's
should start to display the words "logic doubling". If these two text messages are correctly displayed on the CPLD Development/Programmer Board, then you have successfully completed this tutorial.
(12) Select LPT port number
(13) Select cable type
(14) Click on the RUN button
Installation Guide for ProChip Designer 4.0
Installation Guide for ProChip Designer® Version 4.0
Thank you for choosing Atmel ProChip Designer. This document provides the instructions for installing or
updating ProChip Designer and other related PLD software.
I. Installing ProChip Designer from EPLD Software CD.
II. Installing ProChip Designer Trial Version from Atmel Website (PCDTrial.ZIP).
III. Installing ProChip Designer Full License Version from Atmel FTP Site
(PCDPermanent.ZIP).
IV. Updating ProChip Designer with the Patch file (PROCHIPUPDATE.PAT).
V. Installing and setting up Mentor Graphics LeonardoSpectrum.
VI. Installing Mentor Graphics ModelSim.
IMPORTANT:
1. After installing ProChip Designer, the PC must be re-started.
2. ProChip Designer cannot be installed onto PC's that already have either Accolade PeakFPGA or
Protel Design Explorer from Altium (formerly Protel International) installed. Please either uninstall
these software before installing ProChip Designer or install ProChip Designer onto a different PC.
3. Reinstalling ProChip Designer Trial version IS NOT ALLOWED even if the 30-day trial period has not
expired.
4. During the installation of ProChip Designer, both the PeakFPGA and Protel99SE software must be
installed in order for ProChip Designer to work properly.
5. For PCs with WinNT4.0 or Win2000 operating system, users must have permission to modify system
files in order to install ProChip Designer.
6. ProChip Designer cannot be installed into a directory with space(s) in any part of the directory
name (e.g. C:\Program Files).
7. During the installation of PeakFPGA, users must select PeakFPGA Design Suite (VHDL,
Simulation and Synthesis) in the PeakFPGA Design Suite Installation options dialog box.
8. Only LeonardoSpectrum with a LEVEL 3 (mufti-vendor) license will work with ProChip Designer.
9. For designers using Mentor Graphics LeonardoSpectrum, the Atmel CPLD library MUST be setup
again as described in Section V (Setup Library for Mentor Graphics LeonardoSpectrum) after
installing the ProChip Designer Patch (RPOCHIPUDPATE.PAT).
10. For Full License users, the same Access Code should be used for both the PeakFPGA and
Protel99SE software.
11. For Full License software users, the same Access Code used for the ProChip Designer V3.0 Full
License software can be used for V4.0. Please make sure that the Access Code is available before
uninstalling ProChip Designer V3.0. To retrieve the Access Code:
a. Launch PeakFPGA independently or through ProChip Designer.
b. Open an existing project or create a new project.
c. Select the Options System menu item
d. Select the Registration tab and save the PeakFPGA serial number. This is your Access Code.
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA
I. Installing ProChip Designer from EPLD Software CD
Install ProChip Designer Trial version onto PC's that have never had neither the Full License
nor Trial version of ProChip Designer installed:
1. From the "Install Products" screen, click on the PROCHIP DESIGNER ~ 30 DAY TRIAL button.
Install ProChip Designer V4.0 Full License version onto PC's that have never had neither the
Full License nor Trial version of ProChip Designer installed:
1. From the "Install Products" screen, click on the PROCHIP DESIGNER ~ FULL LICENSE button.
Note: An Access Code (Permanent License) is required to install the Full License version software.
This can be obtained by contacting your Atmel Sales Representative or Distributor.
Update ProChip Designer V3.0 or V4.0 Trial version to ProChip Designer V4.0 Full version
or update ProChip Designer V3.0 Full version to ProChip Designer V4.0 Full version
or uninstall ProChip Designer V4.0 Full version and reinstall ProChip Designer V4.0 Full version
1. Remove PeakFPGA using Control Panel Add\Remove Program.
2. Remove Protel 99SE using Control Panel Add\Remove Program.
3. Remove ProChip Designer using Control Panel Add\Remove Program.
4. Manually delete the entire ProChip Designer folder. THIS IS REQUIRED. The default location is
"C:\PROCHIP".
5. Install ProChip Designer Full version. From the "Install Products" screen, click on PROCHIP
DESIGNER ~ FULL LICENSE button.
Note: An Access Code (Permanent License) is required to install the Full License version software.
This can be obtained by contacting your Atmel Sales Representative or Distributor.
Uninstall ProChip Designer V3.0 or V4.0 Trial version and reinstall ProChip Designer V3.0 or
V4.0 Trial version.
Reinstalling ProChip Designer Trial version IS NOT ALLOWED even though the 30-day trial period has
not expired.
II. Installing ProChip Designer Trial Version from Atmel Website - PCDTrial.ZIP
Installing ProChip Designer Trial Version onto PC's that have never had neither the Full License
nor Trial version of ProChip Designer installed:
1. Register on-line at http://www.atmel.com/atmel/products/prod2r.htm, and then download
PCDTrial.ZIP from our website.
2. Use WinZip to extract ZIP file. The file PROCHIP40.EXE will be extracted.
3. Double-click on PROCHIP40.EXE in Windows Explorer to start the installation process.
4. Follow the instructions in the Install shield Wizard throughout the installation process.
5. When installation is completed, re-start PC.
Note: Reinstalling ProChip Designer Trial version IS NOT ALLOWED even if the 30-day trial period
has not expired.
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA
III. Installing/Updating ProChip Designer Full License Version from Atmel FTP
Site - PCDPermanent.ZIP
Installing ProChip Designer Full License Version onto PC's that have never had neither the Full
License nor Trial version of ProChip Designer installed:
1. Obtain Permanent License from Atmel.
2. Download "pcdpermanent.zip" from Atmel FTP Site at ftp://www.atmel.com/pub/atmel.
3. Use WinZip to extract ZIP file.
4. Double-click on PROCHIP40.EXE in Windows Explorer to start the installation process.
5. Follow the instructions in the Install shield Wizard throughout the installation process.
6. When installation is completed, re-start PC.
Updating ProChip Designer V3.0 or V4.0 Trial Version to ProChip Designer V4.0 Full Version
or updating ProChip Designer V3.0 Full Version to ProChip Designer V4.0 Full Version
or reinstalling ProChip Designer V4.0 Full Version
1. Remove PeakFPGA using Control Panel Add\Remove Program.
2. Remove Protel 99SE using Control Panel Add\Remove Program.
3. Remove ProChip Designer using Control Panel Add\Remove Program.
4. Manually delete the entire ProChip Designer folder. THIS IS REQUIRED. The default location is
"C:\PROCHIP".
5. Install ProChip Designer V4.0 Full version. Double-click on PROCHIP40.EXE in Windows Explorer
to start the installation process.
6. When installation is completed, re-start PC.
Note: An Access Code (Permanent License) is required to install the Full License version software.
This can be obtained by contacting your Atmel Sales Representative or Distributor.
IV. To update ProChip Designer V4.0 with the Patch file - PROCHIPUPDATE.PAT:
Update ProChip Designer via Atmel website
1. Launch ProChip Designer.
2. Select the Help Update Via Web menu item to install the latest updates on-line.
Note: Internet connection is required to execute this command.
Update ProChip Designer via file
1. Launch ProChip Designer.
2. Download the file "PROCHIPUPDATE.PAT" from Atmel's website at
http://www.atmel.com/atmel/products/prod147.htm to the [~\Prochip\updates] folder.
3. Select the Help Update Via File menu item. Then select the downloaded
"PROCHIPUPDATE.PAT" file and answer 'Yes' to save the image at the end of the update
process.
Note: For designers using Mentor Graphics LeonardoSpectrum, the Atmel CPLD library MUST be setup
again as described in Section V (Setup Library for Mentor Graphics LeonardoSpectrum) after
installing the ProChip Designer Patch (RPOCHIPUDPATE.PAT).
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA
V. To install and setup Mentor Graphics LeonardoSpectrum:
Install Mentor Graphics LeonardoSpectrum
1. From the "Install Products" screen, click on the LeonardoSpectrum - Evaluation button.
Note: If a regular full license for LeonardoSpectrum Level 3 is available, then Steps 2 to 3 below can
be skipped.
2. Upon the completion of the software installation, the web browser will launch automatically bringing
the users to the Mentor Graphics' Evaluation License Registration site.
3. Fill out all the required fields and click on the "I agree" button at the bottom of this page.
Note: If you had previously requested an Evaluation License from Mentor Graphics for
LeonardoSpectrum, you cannot request for another Evaluation License again. You will have to
purchase a license from Mentor Graphics in order to use LeonardoSpectrum with ProChip Designer.
4. After receiving the license file from Mentor Graphics via email, follow the license setup instructions
provided in the email.
5. Follow the instructions provided in the "Setup Library for Mentor Graphics LeonardoSpectrum"
section below.
Setup Library for Mentor Graphics LeonardoSpectrum
1. Copy 'cpld.syn' from [~\Prochip\Leonardo_update] to [~\MGC\LeoSpec\LS2002c_49\lib].
2. Copy 'atmlcpld.ini' from [~\Prochip\Leonardo_update] to [~\MGC\LeoSpec\LS2002c_49\lib].
3. Copy 'cpld.vhd' from [~\Prochip\Leonardo_update] to [~\MGC\LeoSpec\LS2002c_49\data\modgen].
4. Modify the 'devices.ini' file in the [~\MGC\LeoSpec\LS2002c_49\lib] directory as described below:
a. Attach the line below to the end of device declaration section. The device number "179" is the
last device number plus one. If the last device number in original devices.ini file is a different
number than "178", the device number should be change to appropriate number.
DEVICE_179=atmel_cpld
b. Attach the lines below to the end of devices.ini file.
[atmel_cpld]
CONTACT=EPLD Applications\nATMEL Corporatn\n2325 Orchard Parkway\nSan Jose, CA 95131\n\nTel: (408)
436-4333\nFax: (408) 436-4200\nEmail: pld@atmel.com
DIRECTION=BOTH
FAMILY=CPLD
FORM=FPGA
HTML_PAGE=http://www.atmel.com
INI_FILE=atmlcpld
LIBRARY_NAME=cpld
LICENSE_PACKAGE_NAME=atmel
MANUFACTURER=Atmel
NUMBEROFPASSES=4
PROPTIONS=FALSE
SYMBOL_LIBRARY=none
TECHNOLOGY_TYPE=FPGA
VENDOR_NAME=ATMEL Corporation
BMPFILE=atmel16.bmp
Note: The lines of text above can be copied from the README.TXT file in the
[~\Prochip\Leonardo_update] folder to the DEVICES.INI file.
Note: The Atmel CPLD library MUST be setup again as described above after installing the ProChip
Designer Patch (RPOCHIPUDPATE.PAT).
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA
VI. To install Mentor Graphics ModelSim:
Install Mentor Graphics ModelSim (30-Day Trial Version)
1. From the "Install Products" screen, click on the 30-Day Free trial version of ModelSim button.
2. Click on the Evaluation Edition button in the "Welcome to the ModelSim Install" window.
3. Select YES in the "License Request" window.
4. Fill out all the required fields in the ModelSim SE Evaluation License Request website and then
click on the Request Evaluation button to submit the request.
5. After receiving the license file from Mentor Graphics via email, follow the license setup instructions
provided in the email.
Install Mentor Graphics ModelSim (Full License Version)
1. From the "Install Products" screen, click on the 30-Day Free trial version of ModelSim button.
2. Click on the Full Product button in the "Welcome to the ModelSim Install" window.
3. Select the appropriate license type in the "Select Components" window.
4. Click on the Continue button in the "Model Technology License Wizard" window.
5. Find and select the appropriate license file in the "License File Location" window.
6. If the selected license file is successfully recognized, then click on the Close button to close the "
Model Technology License Wizard" window.
For technical support on Atmel PLD related inquiries, please contact Atmel PLD Applications at:
Hot line : 1-408-436-4333
Email : pld@atmel.com
Logic doubling
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3303A-PLD-08/02 xM
ATMEL® is the registered trademark of Atmel; Atmel-WinCUPL™, Atmel-Synario™ and ProChip Designer™ are
the trademarks of Atmel.
Xilinx® is the registered trademark of Xilinx, Inc. WinSim® is the registered trademark of WinSim, Inc. Altium™
and Design Explorer™ are the trademarks of Altium Limited. Data I/O™ is the trademark of Data I/O Corporation.
Other terms and product names may be the trademarks of others.3303A